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PIC18F1230/1330 Data Sheet
High-Performance Microcontrollers with 10-bit A/D and nanoWatt Technology
2009 Microchip Technology Inc.
DS39758D
Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS39758D-page 2
2009 Microchip Technology Inc.
PIC18F1230/1330
18/20/28-Pin Enhanced Flash Microcontrollers with nanoWatt Technology, High-Performance PWM and A/D
Power-Managed Modes:
* * * * * * * * * * Run: CPU on, peripherals on Idle: CPU off, peripherals on Sleep: CPU off, peripherals off Ultra Low 50 nA Input Leakage Run mode currents down to 15 A, typical Idle mode currents down to 3.7 A, typical Sleep mode current down to 100 nA, typical Timer1 Oscillator: 1.8 A, typical; 32 kHz; 2V Watchdog Timer (WDT): 1.4 A, typical; 2V Two-Speed Oscillator Start-up
Peripheral Highlights:
* * * * High-Current Sink/Source 25 mA/25 mA Up to 4 Programmable External Interrupts Four Input Change Interrupts Enhanced Addressable USART module: - Supports RS-485, RS-232 and LIN/J2602 - RS-232 operation using internal oscillator block (no external crystal required) - Auto-wake-up on Start bit - Auto-Baud Detect 10-Bit, up to 4-Channel Analog-to-Digital Converter module (A/D): - Auto-acquisition capability - Conversion available during Sleep Up to 3 Analog Comparators Programmable Reference Voltage for Comparators Programmable, 15-Level Low-Voltage Detection (LVD) module: - Supports interrupt on Low-Voltage Detection
*
14-Bit Power Control PWM Module:
* Up to 6 PWM Channel Outputs - Complementary or independent outputs * Edge or Center-Aligned Operation * Flexible Dead-Band Generator * Hardware Fault Protection Input * Simultaneous Update of Duty Cycle and Period: - Flexible Special Event Trigger output * * *
Flexible Oscillator Structure:
* Four Crystal modes, up to 40 MHz * 4x Phase Lock Loop (PLL) - Available for Crystal and Internal Oscillators * Two External RC modes, up to 4 MHz - Fast wake-up from Sleep and Idle, 1 s, typical * Two External Clock modes, up to 40 MHz * Internal Oscillator Block: - 8 user-selectable frequencies from 31 kHz to 8 MHz - Provides a complete range of clock speeds from 31 kHz to 32 MHz when used with PLL - User-tunable to compensate for frequency drift * Secondary Oscillator using Timer1 @ 32 kHz * Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops
Program Memory Device Flash # Single-Word (bytes) Instructions 4096 8192 2048 4096 Data Memory SRAM EEPROM (bytes) (bytes) 256 256 128 128 I/O
Special Microcontroller Features:
* C Compiler Optimized Architecture with Optional Extended Instruction Set * Flash Memory Retention: > 40 years * Self-Programmable under Software Control * Priority Levels for Interrupts * 8 x 8 Single-Cycle Hardware Multiplier * Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s * Programmable Code Protection * Single-Supply In-Circuit Serial ProgrammingTM (ICSPTM) via Two Pins * In-Circuit Debug (ICD) via Two Pins * Wide Operating Voltage Range (2.0V to 5.5V)
10-Bit ADC Channel 4 4
EUSART
Analog Comparator 3 3
14-Bit PWM (ch) 6 6
Timers 16-Bit 2 2
PIC18F1230 PIC18F1330
16 16
Yes Yes
2009 Microchip Technology Inc.
DS39758D-page 3
PIC18F1230/1330
Pin Diagrams
18-Pin PDIP, SOIC
RA0/AN0/INT0/KBI0/CMP0 RA1/AN1/INT1/KBI1 RA4/T0CKI/AN2/VREF+ MCLR/VPP/RA5/FLTA(2) VSS/AVSS RA2/TX/CK RA3/RX/DT RB0/PWM0 RB1/PWM1
1 2
18 17
RB3/INT3/KBI3/CMP1/T1OSI(1) RB2/INT2/KBI2/CMP2/T1OSO(1)/T1CKI(1) RA7/OSC1/CLKI/T1OSI(1)/FLTA(2) RA6/OSC2/CLKO/T1OSO(1)/T1CKI(1)/AN3 VDD/AVDD RB7/PWM5/PGD RB6/PWM4/PGC RB5/PWM3 RB4/PWM2
4 5 6 7 8 9
PIC18F1X30
3
16 15 14 13 12 11 10
20-Pin SSOP
RA0/AN0/INT0/KBI0/CMP0 RA1/AN1/INT1/KBI1 RA4/T0CKI/AN2/VREF+ MCLR/VPP/RA5/FLTA(2) VSS AVSS RA2/TX/CK RA3/RX/DT RB0/PWM0 RB1/PWM1
1 2 3
20 19 18
RB3/INT3/KBI3/CMP1/T1OSI(1) RB2/INT2/KBI2/CMP2/T1OSO(1)/T1CKI(1) RA7/OSC1/CLKI/T1OSI(1)/FLTA(2) RA6/OSC2/CLKO/T1OSO(1)/T1CKI(1)/AN3 VDD AVDD RB7/PWM5/PGD RB6/PWM4/PGC RB5/PWM3 RB4/PWM2
PIC18F1X30
4 5 6 7 8 9 10
17 16 15 14 13 12 11
Note 1: 2:
Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H. Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H.
DS39758D-page 4
2009 Microchip Technology Inc.
PIC18F1230/1330
Pin Diagrams (Continued)
28-Pin QFN(3)
RA4/T0CKI/AN2/VREF+ RA1/AN1/INT1/KBI1 RA0/AN0/INT0/KBI0/CMP0 NC RB3/INT3/KBI3/CMP1/T1OSI(1) RB2/INT2/KBI2/CMP2/T1OSO(1)/T1CKI(1) NC 28 27 26 25 24 23 22 MCLR/VPP/RA5/FLTA(2) NC VSS NC AVSS NC RA2/TX/CK 1 2 3 4 5 6 7 21 20 19 18 17 16 15 RA7/OSC1/CLKI/T1OSI(1)/FLTA(2) RA6/OSC2/CLKO/T1OSO(1)/T1CKI(1)/AN3 VDD NC AVDD RB7/PWM5/PGD RB6/PWM4/PGC
PIC18F1X30
8 9 10 11 12 13 14
Note 1: 2: 3:
Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H. Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. It is recommended that the user connect the center metal pad for this device package to the ground.
2009 Microchip Technology Inc.
RA3/RX/DT RB0/PWM0 RB1/PWM1 NC RB4/PWM2 RB5/PWM3 NC
DS39758D-page 5
PIC18F1230/1330
Table of Contents
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 Device Overview .......................................................................................................................................................................... 9 Guidelines for Getting Started with PIC18F Microcontrollers ..................................................................................................... 17 Oscillator Configurations ............................................................................................................................................................ 21 Power-Managed Modes ............................................................................................................................................................. 31 Reset .......................................................................................................................................................................................... 39 Memory Organization ................................................................................................................................................................. 51 Flash Program Memory .............................................................................................................................................................. 71 Data EEPROM Memory ............................................................................................................................................................. 81 8 x 8 Hardware Multiplier............................................................................................................................................................ 85 I/O Ports ..................................................................................................................................................................................... 87 Interrupts .................................................................................................................................................................................... 93 Timer0 Module ......................................................................................................................................................................... 107 Timer1 Module ......................................................................................................................................................................... 111 Power Control PWM Module .................................................................................................................................................... 117 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 147 10-Bit Analog-to-Digital Converter (A/D) Module ..................................................................................................................... 169 Comparator Module.................................................................................................................................................................. 179 Comparator Voltage Reference Module ................................................................................................................................... 183 Low-Voltage Detect (LVD)........................................................................................................................................................ 187 Special Features of the CPU191 21.0 Development Support............................................................................................................................................................... 211 22.0 Instruction Set Summary .......................................................................................................................................................... 215 23.0 Electrical Characteristics .......................................................................................................................................................... 265 24.0 Packaging Information.............................................................................................................................................................. 295 Appendix A: Revision History............................................................................................................................................................. 303 Appendix B: Device Differences......................................................................................................................................................... 304 Appendix C: Conversion Considerations ........................................................................................................................................... 305 Appendix D: Migration from Baseline to Enhanced Devices.............................................................................................................. 305 Appendix E: Migration from Mid-Range TO Enhanced Devices ........................................................................................................ 306 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 306 Index .................................................................................................................................................................................................. 307
DS39758D-page 6
2009 Microchip Technology Inc.
PIC18F1230/1330
TO OUR VALUED CUSTOMERS
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Errata
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2009 Microchip Technology Inc.
DS39758D-page 7
PIC18F1230/1330
NOTES:
DS39758D-page 8
2009 Microchip Technology Inc.
PIC18F1230/1330
1.0 DEVICE OVERVIEW
1.1.2
This document contains device-specific information for the following devices: * PIC18F1230 * PIC18LF1230 * PIC18F1330 * PIC18LF1330
MULTIPLE OSCILLATOR OPTIONS AND FEATURES
All of the devices in the PIC18F1230/1330 family offer ten different oscillator options, allowing users a wide range of choices in developing application hardware. These include: * Four Crystal modes, using crystals or ceramic resonators. * Two External Clock modes, offering the option of using two pins (oscillator input and a divide-by-4 clock output) or one pin (oscillator input, with the second pin reassigned as general I/O). * Two External RC Oscillator modes with the same pin options as the External Clock modes. * An internal oscillator block which provides an 8 MHz clock and an INTRC source (approximately 31 kHz), as well as a range of six user-selectable clock frequencies, between 125 kHz to 4 MHz, for a total of eight clock frequencies. This option frees the two oscillator pins for use as additional general purpose I/Os. * A Phase Lock Loop (PLL) frequency multiplier, available to both the High-Speed Crystal and Internal Oscillator modes, which allows clock speeds of up to 40 MHz. Used with the internal oscillator, the PLL gives users a complete selection of clock speeds, from 31 kHz to 32 MHz, all without using an external crystal or clock circuit. Besides its availability as a clock source, the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: * Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued low-speed operation or a safe application shutdown. * Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset, or wake-up from Sleep mode, until the primary clock source is available.
This family offers the advantages of all PIC18 microcontrollers - namely, high computational performance at an economical price - with the addition of highendurance Enhanced Flash program memory. On top of these features, the PIC18F1230/1330 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power control and motor control applications. Peripheral highlights include: * 14-bit resolution Power Control PWM module (PCPWM) with programmable dead-time insertion The PCPWM can generate up to six complementary PWM outputs with dead-band time insertion. Overdrive current is detected by off-chip analog comparators or the digital Fault input (FLTA). PIC18F1230/1330 devices also feature Flash program memory and an internal RC oscillator.
1.1
1.1.1
New Core Features
nanoWatt TECHNOLOGY
All of the devices in the PIC18F1230/1330 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * Alternate Run Modes: By clocking the controller from the Timer1 source or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. * Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. * On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application's software design. * Low Consumption in Key Modules: The power requirements for both Timer1 and the Watchdog Timer are minimized. See Section 23.0 "Electrical Characteristics" for values.
2009 Microchip Technology Inc.
DS39758D-page 9
PIC18F1230/1330
1.2 Other Special Features 1.3
* Memory Endurance: The Enhanced Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles - up to 100,000 for program memory and 1,000,000 for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. * Self-Programmability: These devices can write to their own program memory spaces under internal software control. By using a bootloader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. * Extended Instruction Set: The PIC18F1230/1330 family introduces an optional extension to the PIC18 instruction set, which adds eight new instructions and an Indexed Addressing mode. This extension, enabled as a device configuration option, has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. * Power Control PWM Module: This module provides up to six modulated outputs for controlling half-bridge and full-bridge drivers. Other features include auto-shutdown on Fault detection and auto-restart to reactivate outputs once the condition has cleared. * Enhanced Addressable USART: This serial communication module is capable of standard RS-232 operation and provides support for the LIN/J2602 bus protocol. Other enhancements include automatic Baud Rate Detection and a 16-bit Baud Rate Generator for improved resolution. When the microcontroller is using the internal oscillator block, the EUSART provides stable operation for applications that talk to the outside world without using an external crystal (or its accompanying power requirement). * 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead. * Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 23.0 "Electrical Characteristics" for time-out periods.
Details on Individual Family Members
Devices in the PIC18F1230/1330 family are available in 18-pin, 20-pin and 28-pin packages. The devices are differentiated from each other in one way: 1. Flash program memory (4 Kbytes PIC18F1230, 8 Kbytes for PIC18F1330). for
All other features for devices in this family are identical. These are summarized in Table 1-1. A block diagram of the PIC18F1220/1320 device architecture is provided in Figure 1-1. The pinouts for this device family are listed in Table 1-2. Like all Microchip PIC18 devices, members of the PIC18F1230/1330 family are available as both standard and low-voltage devices. Standard devices with Enhanced Flash memory, designated with an "F" in the part number (such as PIC18F1330), accommodate an operating VDD range of 4.2V to 5.5V. Low-voltage parts, designated by "LF" (such as PIC18LF1330), function over an extended VDD range of 2.0V to 5.5V.
DS39758D-page 10
2009 Microchip Technology Inc.
PIC18F1230/1330
TABLE 1-1: DEVICE FEATURES
Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Data EEPROM Memory (Bytes) Interrupt Sources I/O Ports Timers Power Control PWM Module Serial Communications 10-Bit Analog-to-Digital Module Resets (and Delays) PIC18F1230 DC - 40 MHz 4096 2048 256 128 17 Ports A, B 2 6 Channels Enhanced USART 4 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes 75 Instructions; 83 with Extended Instruction Set enabled 18-Pin PDIP 18-Pin SOIC 20-Pin SSOP 28-Pin QFN PIC18F1330 DC - 40 MHz 8192 4096 256 128 17 Ports A, B 2 6 Channels Enhanced USART 4 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow (PWRT, OST), MCLR (optional), WDT Yes Yes 75 Instructions; 83 with Extended Instruction Set enabled 18-Pin PDIP 18-Pin SOIC 20-Pin SSOP 28-Pin QFN
Programmable Low-Voltage Detect Programmable Brown-out Reset Instruction Set
Packages
2009 Microchip Technology Inc.
DS39758D-page 11
PIC18F1230/1330
FIGURE 1-1: PIC18F1230/1330 (18-PIN) BLOCK DIAGRAM
Data Bus<8>
21 Table Pointer <2> 21 21 Address Latch Program Memory (4 Kbytes) PIC18F1230 (8 Kbytes) PIC18F1330 Data Latch 16 Table Latch 8 20 inc/dec logic
8
8
8
8
Data Latch Data RAM Address Latch
PORTA RA0/AN0/INT0/KBI0/CMP0 RA1/AN1/INT1/KBI1
PCLATU PCLATH PCU PCH PCL Program Counter 31 Level Stack
12 Address<12> 4 BSR 12 4
RA2/TX/CK RA3/RX/DT RA4/T0CKI/AN2/VREF+ MCLR/VPP/RA5(1)/FLTA(4) RA6/OSC2(2)/CLKO(2)/ T1OSO(3)/T1CKI(3)/AN3 RA7/OSC1(2)/CLKI(2)/ T1OSI(3)/FLTA(4)
FSR0 Bank0, F FSR1 FSR2 12 inc/dec logic
Decode
ROM Latch
PORTB RB0/PWM0
Instruction Register Instruction Decode & Control 3 8 PRODH PRODL 8 x 8 Multiply 8 OSC1(2) OSC2(2) T1OSI T1OSO Timing Generation INTRC Oscillator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Low-Voltage Programming In-Circuit Debugger Brown-out Reset Fail-Safe Clock Monitor Precision Voltage Reference BIT OP 8 WREG 8 8 ALU<8> 8
RB1/PWM1 RB2/INT2/KBI2/CMP2/ T1OSO(3)/T1CKI(3) RB3/INT3/KBI3/CMP1/ T1OSI(3) RB4/PWM2 RB5/PWM3 8 RB6/PWM4/PGC RB7/PWM5/PGD
MCLR(1) VDD, VSS
Timer0
Timer1
PCPWM
BOR LVD
Data EEPROM
10-Bit A/D Converter
Enhanced USART
Note 1: 2: 3: 4:
RA5 is available only when the MCLR Reset is disabled. OSC1, OSC2, CLKI and CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 3.0 "Oscillator Configurations" for additional information. Placement of T1OSI and T1OSO/T1CKI depends on the value of the Configuration bit, T1OSCMX, of CONFIG3H. Placement of FLTA depends on the value of the Configuration bit, FLTAMX, of CONFIG3H.
DS39758D-page 12
2009 Microchip Technology Inc.
PIC18F1230/1330
TABLE 1-2:
Pin Name MCLR/VPP/RA5/FLTA MCLR VPP RA5 FLTA(1) RA7/OSC1/CLKI/ T1OSI/FLTA RA7 OSC1 CLKI T1OSI(2) FLTA(1) RA6/OSC2/CLKO/ T1OSO/T1CKI/AN3 RA6 OSC2 CLKO T1OSO(2) TICKI(2) AN3 15 17 20 I/O O O O I I 16 18 21 I/O I I I I
PIC18F1230/1330 PINOUT I/O DESCRIPTIONS
Pin Number PDIP, SSOP SOIC 4 4 QFN 1 I I I I Pin Type Buffer Type Description
Master Clear (input), programming voltage (input) or Fault detect input. ST Master Clear (Reset) input. This pin is an active-low Reset to the device. Analog Programming voltage input. ST Digital input. ST Fault detect input for PWM. Oscillator crystal, external clock input, Timer1 oscillator input or Fault detect input. ST Digital I/O. Analog Oscillator crystal input or external clock source input. -- External clock source input. Analog Timer1 oscillator input. ST Fault detect input for PWM. Oscillator crystal, clock output, Timer1 oscillator output or analog input. ST Digital I/O. -- Oscillator crystal output or external clock source input. -- External clock source output. -- Timer1 oscillator output. ST Timer1 clock input. Analog Analog input 3.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. 2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H.
2009 Microchip Technology Inc.
DS39758D-page 13
PIC18F1230/1330
TABLE 1-2:
Pin Name
PIC18F1230/1330 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP, SSOP SOIC 1 1 QFN Pin Type Buffer Type Description PORTA is a bidirectional I/O port.
RA0/AN0/INT0/KBI0/ CMP0 RA0 AN0 INT0 KBI0 CMP0 RA1/AN1/INT1/KBI1 RA1 AN1 INT1 KBI1 RA2/TX/CK RA2 TX CK RA3/RX/DT RA3 RX DT RA4/T0CKI/AN2/VREF+ RA4 T0CKI AN2 VREF+
26 I/O I I I I TTL Analog ST TTL Analog TTL Analog ST TTL TTL -- ST TTL ST ST TTL ST Analog Analog Digital I/O. Analog input 0. External interrupt 0. Interrupt-on-change pin. Comparator 0 input. Digital I/O. Analog input 1. External interrupt 1. Interrupt-on-change pin. Digital I/O. EUSART asynchronous transmit. EUSART synchronous clock. Digital I/O. EUSART asynchronous receive. EUSART synchronous data. Digital I/O. Timer0 external clock input. Analog input 2. A/D reference voltage (high) input.
2
2
27 I/O I I I
6
7
7 I/O O I/O
7
8
8 I/O I I/O
3
3
28 I/O I I I
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. 2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H.
DS39758D-page 14
2009 Microchip Technology Inc.
PIC18F1230/1330
TABLE 1-2:
Pin Name
PIC18F1230/1330 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP, SSOP SOIC 8 9 QFN Pin Type Buffer Type Description PORTB is a bidirectional I/O port.
RB0/PWM0 RB0 PWM0 RB1/PWM1 RB1 PWM1 RB2/INT2/KBI2/CMP2/ T1OSO/T1CKI RB2 INT2 KBI2 CMP2 T1OSO(2) T1CKI(2) RB3/INT3/KBI3/CMP1/ T1OSI RB3 INT3 KBI3 CMP1 T1OSI(2) RB4/PWM2 RB4 PWM2 RB5/PWM3 RB5 PWM3 RB6/PWM4/PGC RB6 PWM4 PGC RB7/PWM5/PGD RB7 PWM5 PGD
9 I/O O TTL -- TTL -- Digital I/O. PWM module output PWM0. Digital I/O. PWM module output PWM1.
9
10
10 I/O O
17
19
23 I/O I I I O I TTL ST TTL Analog -- ST Digital I/O. External interrupt 2. Interrupt-on-change pin. Comparator 2 input. Timer1 oscillator output. Timer1 clock input.
18
20
24 I/O I I I I TTL ST TTL Analog Analog TTL -- TTL -- TTL -- ST Digital I/O. External interrupt 3. Interrupt-on-change pin. Comparator 1 input. Timer1 oscillator input. Digital I/O. PWM module output PWM2. Digital I/O. PWM module output PWM3. Digital I/O. PWM module output PWM4. In-Circuit Debugger and ICSPTM programming clock pin. Digital I/O. PWM module output PWM5. In-Circuit Debugger and ICSP programming data pin.
10
11
12 I/O O
11
12
13 I/O O
12
13
15 I/O O I
13
14
16 I/O O O TTL -- --
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. 2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H.
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PIC18F1230/1330
TABLE 1-2:
Pin Name VSS VDD AVSS AVDD NC
PIC18F1230/1330 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number PDIP, SSOP SOIC 5 14 5 14 -- 5 16 6 15 -- QFN 3 19 5 17 2, 4, 6, 11, 14, 18, 22, 25 Pin Type P P P P -- Buffer Type -- -- -- -- -- Description Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. Ground reference for A/D Converter module. Positive supply for A/D Converter module. No Connect.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input O = Output P = Power Note 1: Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. 2: Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H.
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PIC18F1230/1330
2.0 GUIDELINES FOR GETTING STARTED WITH PIC18F MICROCONTROLLERS
Basic Connection Requirements
FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS
C2(1)
2.1
VDD
VDD MCLR
Getting started with the PIC18F1230/1330 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: * All VDD and VSS pins (see Section 2.2 "Power Supply Pins") * All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 "Power Supply Pins") * MCLR pin (see Section 2.3 "Master Clear (MCLR) Pin") These pins must also be connected if they are being used in the end application: * PGC/PGD pins used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes (see Section 2.4 "ICSP Pins") * OSCI and OSCO pins when an external oscillator source is used (see Section 2.5 "External Oscillator Pins") Additionally, the following pins may be required: * VREF+/VREF- pins are used when external voltage reference for analog modules is implemented Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used.
R1 R2
VSS
C1
VDD
PIC18FXXXX
VSS VSS
C3(1)
C6(1)
AVDD VDD AVSS VDD VSS
C5(1)
C4(1)
Key (all values are recommendations): C1 through C6: 0.1 F, 20V ceramic R1: 10 k R2: 100 to 470 Note 1: The example shown is for a PIC18F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately.
The minimum mandatory connections are shown in Figure 2-1.
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PIC18F1230/1330
2.2
2.2.1
Power Supply Pins
DECOUPLING CAPACITORS
2.2.2
TANK CAPACITORS
The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: * Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. * Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). * Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). * Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance.
On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F.
2.2.3
CONSIDERATIONS WHEN USING BOR
When the Brown-out Reset (BOR) feature is enabled, a sudden change in VDD may result in a spontaneous BOR event. This can happen when the microcontroller is operating under normal operating conditions, regardless of what the BOR set point has been programmed to, and even if VDD does not approach the set point. The precipitating factor in these BOR events is a rise or fall in VDD with a slew rate faster than 0.15V/s. An application that incorporates adequate decoupling between the power supplies will not experience such rapid voltage changes. Additionally, the use of an electrolytic tank capacitor across VDD and VSS, as described above, will be helpful in preventing high slew rate transitions. If the application has components that turn on or off, and share the same VDD circuit as the microcontroller, the BOR can be disabled in software by using the SBOREN bit before switching the component. Afterwards, allow a small delay before re-enabling the BOR. By doing this, it is ensured that the BOR is disabled during the interval that might cause high slew rate changes of VDD. Note: Not all devices incorporate software BOR control. See Section 5.0 "Reset" for device-specific information.
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2009 Microchip Technology Inc.
PIC18F1230/1330
2.3 Master Clear (MCLR) Pin 2.4 ICSP Pins
The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application's resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application's requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. The PGC and PGD pins are used for In-Circuit Serial ProgrammingTM (ICSPTM) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100. Pull-up resistors, series diodes, and capacitors on the PGC and PGD pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the "Communication Channel Select" (i.e., PGCx/PGDx pins) programmed into the device matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section 21.0 "Development Support".
FIGURE 2-2:
VDD R1
EXAMPLE OF MCLR PIN CONNECTIONS
R2 JP C1
MCLR PIC18FXXXX
Note 1:
R1 10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R2 470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met.
2:
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PIC18F1230/1330
2.5 External Oscillator Pins
FIGURE 2-3:
Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 "Oscillator Configurations" for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Layout suggestions are shown in Figure 2-4. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. In planning the application's routing and I/O assignments, ensure that adjacent port pins and other signals in close proximity to the oscillator are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): * AN826, "Crystal Oscillator Basics and Crystal Selection for rfPICTM and PICmicro(R) Devices" * AN849, "Basic PICmicro(R) Oscillator Design" * AN943, "Practical PICmicro(R) Oscillator Analysis and Design" * AN949, "Making Your Oscillator Work"
SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
Single-Sided and In-Line Layouts:
Copper Pour (tied to ground) Primary Oscillator Crystal DEVICE PINS
Primary Oscillator C1 C2
OSC1 OSC2 GND T1OSO
Timer1 Oscillator Crystal
T1OS I
T1 Oscillator: C1
T1 Oscillator: C2
Fine-Pitch (Dual-Sided) Layouts:
Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 GND Oscillator Crystal C1 OSCI
2.6
Unused I/Os
DEVICE PINS
Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 k to 10 k resistor to VSS on unused pins and drive the output to logic low.
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PIC18F1230/1330
3.0
3.1
OSCILLATOR CONFIGURATIONS
Oscillator Types
FIGURE 3-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (XT, LP, HS OR HSPLL CONFIGURATION)
OSC1 To Internal Logic Sleep
PIC18F1230/1330 devices can be operated in ten different oscillator modes. The user can program the Configuration bits, FOSC3:FOSC0, in Configuration Register 1H to select one of these ten modes: Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator High-Speed Crystal/Resonator with PLL enabled 5. RC External Resistor/Capacitor with FOSC/4 output on RA6 6. RCIO External Resistor/Capacitor with I/O on RA6 7. INTIO1 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 8. INTIO2 Internal Oscillator with I/O on RA6 and RA7 9. EC External Clock with FOSC/4 output 10. ECIO External Clock with I/O on RA6 1. 2. 3. 4. LP XT HS HSPLL
C1(1)
XTAL
RS(2) C2(1) Note 1: 2: 3: OSC2
RF(3)
PIC18FXXXX
See Table 3-1 and Table 3-2 for initial values of C1 and C2. A series resistor (RS) may be required for AT strip cut crystals. RF varies with the oscillator mode chosen.
TABLE 3-1:
CAPACITOR SELECTION FOR CERAMIC RESONATORS
Typical Capacitor Values Used: Mode XT Freq 3.58 MHz 4.19 MHz 4 MHz 4 MHz OSC1 15 pF 15 pF 30 pF 50 pF OSC2 15 pF 15 pF 30 pF 50 pF
3.2
Crystal Oscillator/Ceramic Resonators
In XT, LP, HS or HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 3-1 shows the pin connections. The oscillator design requires the use of a parallel resonant crystal. Note: Use of a series resonant crystal may give a frequency out of the crystal manufacturer's specifications.
Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table 3-2 for additional information.
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PIC18F1230/1330
TABLE 3-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR
Crystal Freq 32 kHz 1 MHz 4 MHz 4 MHz 10 MHz 20 MHz 25 MHz Typical Capacitor Values Tested: C1 LP XT HS 30 pF 15 pF 15 pF 15 pF 15 pF 15 pF 15 pF C2 30 pF 15 pF 15 pF 15 pF 15 pF 15 pF 15 pF
Clock from Ext. System Open
An external clock source may also be connected to the OSC1 pin in the HS mode, as shown in Figure 3-2.
FIGURE 3-2:
Osc Type
EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION)
OSC1
PIC18FXXXX
OSC2 (HS Mode)
Capacitor values are for design guidance only. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information.
3.3
External Clock Input
The EC and ECIO Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-3 shows the pin connections for the EC Oscillator mode.
Note 1: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 2: When operating below 3V VDD, or when using certain ceramic resonators at any voltage, it may be necessary to use the HS mode or switch to a crystal oscillator. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required to avoid overdriving crystals with low drive level specification. 5: Always verify oscillator performance over the VDD and temperature range that is expected for the application.
FIGURE 3-3:
EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION)
OSC1/CLKI
Clock from Ext. System FOSC/4
PIC18FXXXX
OSC2/CLKO
The ECIO Oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 3-4 shows the pin connections for the ECIO Oscillator mode.
FIGURE 3-4:
EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)
OSC1/CLKI
Clock from Ext. System RA6
PIC18FXXXX
I/O (OSC2)
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2009 Microchip Technology Inc.
PIC18F1230/1330
3.4 RC Oscillator 3.5 PLL Frequency Multiplier
For timing insensitive applications, the "RC" and "RCIO" device options offer additional cost savings. The actual oscillator frequency is a function of several factors: * supply voltage * values of the external resistor (REXT) and capacitor (CEXT) * operating temperature Given the same device, operating voltage and temperature and component values, there will also be unit-to-unit frequency variations. These are due to factors such as: * normal manufacturing variation * difference in lead frame capacitance between package types (especially for low CEXT values) * variations within the tolerance of limits of REXT and CEXT In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-5 shows how the R/C combination is connected. A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator.
3.5.1
HSPLL OSCILLATOR MODE
The HSPLL mode makes use of the HS mode oscillator for frequencies up to 10 MHz. A PLL then multiplies the oscillator output frequency by 4 to produce an internal clock frequency up to 40 MHz. The PLLEN bit is not available in this oscillator mode. The PLL is only available to the crystal oscillator when the FOSC3:FOSC0 Configuration bits are programmed for HSPLL mode (= 0110).
FIGURE 3-7:
PLL BLOCK DIAGRAM (HS MODE)
HS Oscillator Enable PLL Enable (from Configuration Register 1H) OSC2
HS Mode OSC1 Crystal Osc
FIGURE 3-5:
VDD REXT
RC OSCILLATOR MODE
FIN FOUT
Phase Comparator
OSC1 CEXT VSS FOSC/4 OSC2/CLKO
Internal Clock
Loop Filter
PIC18FXXXX
4 VCO MUX SYSCLK
Recommended values: 3 k REXT 100 k CEXT > 20 pF
The RCIO Oscillator mode (Figure 3-6) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6).
3.5.2
PLL AND INTOSC
FIGURE 3-6:
VDD REXT
RCIO OSCILLATOR MODE
OSC1 CEXT VSS RA6 I/O (OSC2)
Internal Clock
The PLL is also available to the internal oscillator block in selected oscillator modes. In this configuration, the PLL is enabled in software and generates a clock output of up to 32 MHz. The operation of INTOSC with the PLL is described in Section 3.6.4 "PLL in INTOSC Modes".
PIC18FXXXX
Recommended values: 3 k REXT 100 k CEXT > 20 pF
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PIC18F1230/1330
3.6 Internal Oscillator Block
The PIC18F1230/1330 devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller's clock source. This may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the device clock. It also drives a postscaler, which can provide a range of clock frequencies from 31 kHz to 4 MHz. The INTOSC output is enabled when a clock frequency from 125 kHz to 8 MHz is selected. The other clock source is the internal RC oscillator (INTRC), which provides a nominal 31 kHz output. INTRC is enabled if it is selected as the device clock source; it is also enabled automatically when any of the following are enabled: * * * * Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. The OSCTUNE register also implements the INTSRC and PLLEN bits, which control certain features of the internal oscillator block. The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31 kHz frequency option is selected. This is covered in greater detail in Section 3.7.1 "Oscillator Control Register". The PLLEN bit controls the operation of the frequency multiplier, PLL, in internal oscillator modes.
3.6.4
PLL IN INTOSC MODES
The 4x frequency multiplier can be used with the internal oscillator block to produce faster device clock speeds than are normally possible with an internal oscillator. When enabled, the PLL produces a clock speed of up to 32 MHz. Unlike HSPLL mode, the PLL is controlled through software. The control bit, PLLEN (OSCTUNE<6>), is used to enable or disable its operation. If PLL is enabled and a Two-Speed Start-up from wake is performed, execution is delayed until the PLL starts. The PLL is available when the device is configured to use the internal oscillator block as its primary clock source (FOSC3:FOSC0 = 1001 or 1000). Additionally, the PLL will only function when the selected output frequency is either 4 MHz or 8 MHz (OSCCON<6:4> = 111 or 110). If both of these conditions are not met, the PLL is disabled. The PLLEN control bit is only functional in those internal oscillator modes where the PLL is available. In all other modes, it is forced to `0' and is effectively unavailable.
These features are discussed in greater detail in Section 20.0 "Special Features of the CPU". The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 28).
3.6.1
INTIO MODES
Using the internal oscillator as the clock source eliminates the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available: * In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. * In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output.
3.6.5
INTOSC FREQUENCY DRIFT
3.6.2
INTOSC OUTPUT FREQUENCY
The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz. The INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa.
The factory calibrates the internal oscillator block output (INTOSC) for 8 MHz. However, this frequency may drift as VDD or temperature changes, which can affect the controller operation in a variety of ways. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency. Tuning the INTOSC source requires knowing when to make the adjustment, in which direction it should be made and in some cases, how large a change is needed. Two compensation techniques are discussed in Section 3.6.5.1 "Compensating with the EUSART" and Section 3.6.5.2 "Compensating with the Timers", but other techniques may be used.
3.6.3
OSCTUNE REGISTER
The internal oscillator's output has been calibrated at the factory but can be adjusted in the user's application. This is done by writing to the OSCTUNE register (Register 3-1). The tuning sensitivity is constant throughout the tuning range.
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PIC18F1230/1330
REGISTER 3-1:
R/W-0 INTSRC bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OSCTUNE: OSCILLATOR TUNING REGISTER
R/W-0(1) PLLEN(1) U-0 -- R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled) 0 = 31 kHz device clock derived directly from INTRC internal oscillator PLLEN: Frequency Multiplier PLL for INTOSC Enable bit(1) 1 = PLL enabled for INTOSC (4 MHz and 8 MHz only) 0 = PLL disabled Unimplemented: Read as `0' TUN4:TUN0: Frequency Tuning bits 01111 = Maximum frequency * * * * 00001 00000 = Center frequency. Oscillator module is running at the calibrated frequency. 11111 * * * * 10000 = Minimum frequency Available only in certain oscillator configurations; otherwise, this bit is unavailable and reads as `0'. See Section 3.6.4 "PLL in INTOSC Modes" for details.
bit 6
bit 5 bit 4-0
Note 1:
3.6.5.1
Compensating with the EUSART
3.6.5.2
Compensating with the Timers
An adjustment may be required when the EUSART begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high; to adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment OSCTUNE to increase the clock frequency.
This technique compares device clock speed to some reference clock. Two timers may be used; one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register.
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PIC18F1230/1330
3.7 Clock Sources and Oscillator Switching
The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. PIC18F1230/1330 devices offer the Timer1 oscillator as a secondary oscillator. This oscillator, in all powermanaged modes, is often the time base for functions such as a real-time clock. Most often, a 32.768 kHz watch crystal is connected between the T1OSO/T1CKI and T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 13.2 "Timer1 Oscillator". In addition to being a primary clock source, the internal oscillator block is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F1230/1330 devices are shown in Figure 3-8. See Section 20.0 "Special Features of the CPU" for Configuration register details.
Like previous PIC18 devices, the PIC18F1230/1330 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F1230/1330 devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available. Essentially, there are three clock sources for these devices: * Primary oscillators * Secondary oscillators * Internal oscillator block The primary oscillators include the External Crystal and Resonator modes, the External RC modes, the External Clock modes and the internal oscillator block. The particular mode is defined by the FOSC3:FOSC0 Configuration bits. The details of these modes are covered earlier in this chapter.
FIGURE 3-8:
PIC18F1230/1330 CLOCK DIAGRAM
Primary Oscillator OSC2 Sleep OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator OSCCON<6:4> Internal Oscillator Block 8 MHz Source INTRC Source OSCTUNE<6> 4 x PLL
LP, XT, HS, RC, EC HSPLL, INTOSC/PLL T1OSC Peripherals
T1OSI
OSCCON<6:4> 8 MHz 4 MHz 2 MHz Postscaler 1 MHz 500 kHz 250 kHz 125 kHz 111 110 101 100 011 010 001 MUX
Internal Oscillator CPU
MUX
IDLEN Clock Control FOSC3:FOSC0 OSCCON<1:0>
8 MHz (INTOSC)
31 kHz (INTRC)
1 31 kHz 000 0 OSCTUNE<7>
Clock Source Option for Other Modules
WDT, PWRT, FSCM and Two-Speed Start-up
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PIC18F1230/1330
3.7.1 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 3-2) controls several aspects of the device clock's operation, both in full power operation and in power-managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source. The available clock sources are the primary clock (defined by the FOSC3:FOSC0 Configuration bits), the secondary clock (Timer1 oscillator) and the internal oscillator block. The clock source changes immediately after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared on all forms of Reset. The Internal Oscillator Frequency Select bits (IRCF2:IRCF0) select the frequency output of the internal oscillator block to drive the device clock. The choices are the INTRC source, the INTOSC source (8 MHz) or one of the frequencies derived from the INTOSC postscaler (31.25 kHz to 4 MHz). If the internal oscillator block is supplying the device clock, changing the states of these bits will have an immediate change on the internal oscillator's output. On device Resets, the default output frequency of the internal oscillator block is set at 1 MHz. When a nominal output frequency of 31 kHz is selected (IRCF2:IRCF0 = 000), users may choose which internal oscillator acts as the source. This is done with the INTSRC bit in the OSCTUNE register (OSCTUNE<7>). Setting this bit selects INTOSC as a 31.25 kHz clock source by enabling the divide-by-256 output of the INTOSC postscaler. Clearing INTSRC selects INTRC (nominally 31 kHz) as the clock source. This option allows users to select the tunable and more precise INTOSC as a clock source, while maintaining power savings with a very low clock speed. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the Watchdog Timer and the Fail-Safe Clock Monitor. The OSTS, IOFS and T1RUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer has timed out and the primary clock is providing the device clock in primary clock modes. The IOFS bit indicates when the internal oscillator block has stabilized and is providing the device clock in RC Clock modes. The T1RUN bit (T1CON<6>) indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these three bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed. The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 4.0 "Power-Managed Modes". Note 1: The Timer1 oscillator must be enabled to select the secondary clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON<3>). If the Timer1 oscillator is not enabled, then any attempt to select a secondary clock source will be ignored. 2: It is recommended that the Timer1 oscillator be operating and stable before selecting the secondary clock source or a very long delay may occur while the Timer1 oscillator starts.
3.7.2
OSCILLATOR TRANSITIONS
PIC18F1230/1330 devices contain circuitry to prevent clock "glitches" when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in greater detail in Section 4.1.2 "Entering Power-Managed Modes".
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REGISTER 3-2:
R/W-0 IDLEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-1 IRCF2 R/W-0 IRCF1 R/W-0 IRCF0 R(1) OSTS R-0 IOFS R/W-0 SCS1 R/W-0 SCS0 bit 0
IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction IRCF2:IRCF0: Internal Oscillator Frequency Select bits 111 = 8 MHz (INTOSC drives clock directly) 110 = 4 MHz 101 = 2 MHz 100 = 1 MHz(3) 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (from either INTOSC/256 or INTRC directly)(2) OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready IOFS: INTOSC Frequency Stable bit 1 = INTOSC frequency is stable 0 = INTOSC frequency is not stable SCS1:SCS0: System Clock Select bits 1x = Internal oscillator block 01 = Secondary (Timer1) oscillator 00 = Primary oscillator Reset state depends on state of the IESO Configuration bit. Source selected by the INTSRC bit (OSCTUNE<7>), see text. Default output frequency of INTOSC on Reset.
bit 6-4
bit 3
bit 2
bit 1-0
Note 1: 2: 3:
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3.8 Effects of Power-Managed Modes on the Various Clock Sources
time clock. Other features may be operating that do not require a device clock source (i.e., INTx pins and others). Peripherals that may add significant current consumption are listed in Section 23.0 "Electrical Characteristics".
When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1 or Timer3. In internal oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the device clock source. The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features, regardless of the powermanaged mode (see Section 20.2 "Watchdog Timer (WDT)", Section 20.3 "Two-Speed Start-up" and Section 20.4 "Fail-Safe Clock Monitor" for more information on WDT, Fail-Safe Clock Monitor and TwoSpeed Start-up). The INTOSC output at 8 MHz may be used directly to clock the device or may be divided down by the postscaler. The INTOSC output is disabled if the clock is provided directly from the INTRC output. If the Sleep mode is selected, all clock sources are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support a real-
3.9
Power-up Delays
Power-up delays are controlled by two timers, so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 5.5 "Device Reset Timers". The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 23-10). It is enabled by clearing (= 0) the PWRTEN Configuration bit. The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (LP, XT and HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. When the HSPLL Oscillator mode is selected, the device is kept in Reset for an additional 2 ms, following the HS mode OST delay, so the PLL can lock to the incoming clock frequency. There is a delay of interval TCSD (parameter 38, Table 23-10), following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the EC, RC or INTIO modes are used as the primary clock source.
TABLE 3-3:
RC, INTIO1 RCIO INTIO2 ECIO EC LP, XT and HS Note:
OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC1 Pin Floating, external resistor should pull high Floating, external resistor should pull high Configured as PORTA, bit 7 Floating, pulled by external clock Floating, pulled by external clock Feedback inverter disabled at quiescent voltage level OSC2 Pin At logic low (clock/4 output) Configured as PORTA, bit 6 Configured as PORTA, bit 6 Configured as PORTA, bit 6 At logic low (clock/4 output) Feedback inverter disabled at quiescent voltage level
Oscillator Mode
See Table 5-2 in Section 5.0 "Reset" for time-outs due to Sleep and MCLR Reset.
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NOTES:
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4.0 POWER-MANAGED MODES
4.1.1 CLOCK SOURCES
PIC18F1230/1330 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices). There are three categories of power-managed modes: * Run modes * Idle modes * Sleep mode These categories define which portions of the device are clocked and sometimes, what speed. The Run and Idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the Sleep mode does not use a clock source. The power-managed modes include several powersaving features offered on previous PIC(R) devices. One is the clock switching feature, offered in other PIC18 devices, allowing the controller to use the Timer1 oscillator in place of the primary oscillator. Also included is the Sleep mode, offered by all PIC devices, where all device clocks are stopped. The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: * the primary clock, as defined by the FOSC3:FOSC0 Configuration bits * the secondary clock (the Timer1 oscillator) * the internal oscillator block (for RC modes)
4.1.2
ENTERING POWER-MANAGED MODES
Switching from one power-managed mode to another begins by loading the OSCCON register. The SCS1:SCS0 bits select the clock source and determine which Run or Idle mode is to be used. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch may also be subject to clock transition delays. These are discussed in Section 4.1.3 "Clock Transitions and Status Indicators" and subsequent sections. Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, or changing the IDLEN bit, prior to issuing a SLEEP instruction. If the IDLEN bit is already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode.
4.1
Selecting Power-Managed Modes
Selecting a power-managed mode requires two decisions: if the CPU is to be clocked or not and the selection of a clock source. The IDLEN bit (OSCCON<7>) controls CPU clocking, while the SCS1:SCS0 bits (OSCCON<1:0>) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 4-1.
TABLE 4-1:
Mode Sleep PRI_RUN
POWER-MANAGED MODES
OSCCON Bits IDLEN<7>(1) 0 N/A SCS1:SCS0 <1:0> N/A 00 Module Clocking Available Clock and Oscillator Source CPU Off Clocked Peripherals Off Clocked None - All clocks are disabled Primary - LP, XT, HS, HSPLL, RC, EC and Internal Oscillator Block(2). This is the normal full power execution mode. Secondary - Timer1 Oscillator Internal Oscillator Block(2) Primary - LP, XT, HS, HSPLL, RC, EC Secondary - Timer1 Oscillator Internal Oscillator Block(2)
SEC_RUN RC_RUN PRI_IDLE SEC_IDLE RC_IDLE Note 1: 2:
N/A N/A 1 1 1
01 1x 00 01 1x
Clocked Clocked Off Off Off
Clocked Clocked Clocked Clocked Clocked
IDLEN reflects its value when the SLEEP instruction is executed. Includes INTOSC and INTOSC postscaler, as well as the INTRC source.
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4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS
4.2
Run Modes
The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Three bits indicate the current clock source and its status. They are: * OSTS (OSCCON<3>) * IOFS (OSCCON<2>) * T1RUN (T1CON<6>) In general, only one of these bits will be set while in a given power-managed mode. When the OSTS bit is set, the primary clock is providing the device clock. When the IOFS bit is set, the INTOSC output is providing a stable 8 MHz clock source to a divider that actually drives the device clock. When the T1RUN bit is set, the Timer1 oscillator is providing the clock. If none of these bits are set, then either the INTRC clock source is clocking the device, or the INTOSC source is not yet stable. If the internal oscillator block is configured as the primary clock source by the FOSC3:FOSC0 Configuration bits, then both the OSTS and IOFS bits may be set when in PRI_RUN or PRI_IDLE modes. This indicates that the primary clock (INTOSC output) is generating a stable 8 MHz output. Entering another power-managed RC mode at the same frequency would clear the OSTS bit. Note 1: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated. 2: Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep mode or one of the Idle modes, depending on the setting of the IDLEN bit.
In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source.
4.2.1
PRI_RUN MODE
The PRI_RUN mode is the normal, full power execution mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up is enabled (see Section 20.3 "Two-Speed Start-up" for details). In this mode, the OSTS bit is set. The IOFS bit may be set if the internal oscillator block is the primary clock source (see Section 3.7.1 "Oscillator Control Register").
4.2.2
SEC_RUN MODE
The SEC_RUN mode is the compatible mode to the "clock switching" feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of lower power consumption while still using a high accuracy clock source. SEC_RUN mode is entered by setting the SCS1:SCS0 bits to `01'. The device clock source is switched to the Timer1 oscillator (see Figure 4-1), the primary oscillator is shut down, the T1RUN bit (T1CON<6>) is set and the OSTS bit is cleared. Note: The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS1:SCS0 bits are set to `01', entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result.
4.1.4
MULTIPLE SLEEP COMMANDS
The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN at that time. If IDLEN has changed, the device will enter the new power-managed mode specified by the new setting.
On transitions from SEC_RUN to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run.
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FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE
Q1 Q2 Q3 Q4 Q1 T1OSI OSC1 CPU Clock Peripheral Clock Program Counter 1 2 3 n-1 n Q2 Q3 Q4 Q1 Q2 Q3
Clock Transition(1)
PC
PC + 2
PC + 4
Note 1:
Clock transition typically occurs within 2-4 TOSC.
FIGURE 4-2:
TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL)
Q1 T1OSI OSC1 TOST(1) TPLL(1) 1 2 n-1 n Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed PC OSTS bit Set
Clock Transition(2)
PC + 2
PC + 4
Note 1: 2:
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. Clock transition typically occurs within 2-4 TOSC.
4.2.3
RC_RUN MODE
In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator block using the INTOSC multiplexer. In this mode, the primary clock is shut down. When using the INTRC source, this mode provides the best power conservation of all the Run modes, while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times. If the primary clock source is the internal oscillator block (either INTRC or INTOSC), there are no distinguishable differences between PRI_RUN and RC_RUN modes during execution. However, a clock switch delay will occur during entry to and exit from RC_RUN mode. Therefore, if the primary clock source is the internal oscillator block, the use of RC_RUN mode is not recommended.
This mode is entered by setting the SCS1 bit to `1'. Although it is ignored, it is recommended that the SCS0 bit also be cleared; this is to maintain software compatibility with future devices. When the clock source is switched to the INTOSC multiplexer (see Figure 4-3), the primary oscillator is shut down and the OSTS bit is cleared. The IRCF bits may be modified at any time to immediately change the clock speed. Note: Caution should be used when modifying a single IRCF bit. If VDD is less than 3V, it is possible to select a higher clock speed than is supported by the low VDD. Improper device operation may result if the VDD/FOSC specifications are violated.
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If the IRCF bits and the INTSRC bit are all clear, the INTOSC output is not enabled and the IOFS bit will remain clear; there will be no indication of the current clock source. The INTRC source is providing the device clocks. If the IRCF bits are changed from all clear (thus, enabling the INTOSC output), or if INTSRC is set, the IOFS bit becomes set after the INTOSC output becomes stable. Clocks to the device continue while the INTOSC source stabilizes after an interval of TIOBST. If the IRCF bits were previously at a non-zero value, or if INTSRC was set before setting SCS1 and the INTOSC source was already stable, the IOFS bit will remain set. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4). When the clock switch is complete, the IOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled.
FIGURE 4-3:
TRANSITION TIMING TO RC_RUN MODE
Q1 Q2 Q3 Q4 Q1 Q2 1 2 3 n-1 n Q3 Q4 Q1 Q2 Q3
INTRC OSC1 CPU Clock Peripheral Clock Program Counter PC
Clock Transition(1)
PC + 2
PC + 4
Note 1:
Clock transition typically occurs within 2-4 TOSC.
FIGURE 4-4:
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
INTOSC Multiplexer OSC1 TOST(1) PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS1:SCS0 bits Changed PC OSTS bit Set PC + 2 PC + 4 TPLL(1) 1 2 n-1 n
Clock Transition(2)
Note 1: 2:
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. Clock transition typically occurs within 2-4 TOSC.
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4.3 Sleep Mode 4.4 Idle Modes
The power-managed Sleep mode in the PIC18F1230/ 1330 devices is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS1:SCS0 bits becomes ready (see Figure 4-6), or it will be clocked from the internal oscillator block if either the Two-Speed Start-up or the Fail-Safe Clock Monitor are enabled (see Section 20.0 "Special Features of the CPU"). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. The Idle modes allow the controller's CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a `1' when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS1:SCS0 bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (parameter 38, Table 23-10) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits.
FIGURE 4-5:
OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
PC + 2
FIGURE 4-6:
OSC1 PLL Clock Output CPU Clock Peripheral Clock Program Counter
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST(1)
TPLL(1)
PC Wake Event OSTS bit Set
PC + 2
PC + 4
PC + 6
Note1:TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
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4.4.1 PRI_IDLE MODE
This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to "warm-up" or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then clear the SCS bits and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC3:FOSC0 Configuration bits. The OSTS bit remains set (see Figure 4-7). When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval TCSD is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wakeup, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 4-8). setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set the IDLEN bit first, then set the SCS1:SCS0 bits to `01' and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the T1RUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After an interval of TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run (see Figure 4-8). Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result.
4.4.2
SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by
FIGURE 4-7:
TRANSITION TIMING FOR ENTRY TO IDLE MODE
Q1 Q2 Q3 Q4 Q1
OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2
FIGURE 4-8:
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Q1 Q2 Q3 Q4
OSC1 CPU Clock Peripheral Clock Program Counter Wake Event PC TCSD
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4.4.3 RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block using the INTOSC multiplexer. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP. Although its value is ignored, it is recommended that SCS0 also be cleared; this is to maintain software compatibility with future devices. The INTOSC multiplexer may be used to select a higher clock frequency by modifying the IRCF bits before executing the SLEEP instruction. When the clock source is switched to the INTOSC multiplexer, the primary oscillator is shut down and the OSTS bit is cleared. If the IRCF bits are set to any non-zero value, or the INTSRC bit is set, the INTOSC output is enabled. The IOFS bit becomes set, after the INTOSC output becomes stable, after an interval of TIOBST (parameter 39, Table 23-10). Clocks to the peripherals continue while the INTOSC source stabilizes. If the IRCF bits were previously at a non-zero value, or INTSRC was set before the SLEEP instruction was executed and the INTOSC source was already stable, the IOFS bit will remain set. If the IRCF bits and INTSRC are all clear, the INTOSC output will not be enabled, the IOFS bit will remain clear and there will be no indication of the current clock source. When a wake event occurs, the peripherals continue to be clocked from the INTOSC multiplexer. After a delay of TCSD following the wake event, the CPU begins executing code being clocked by the INTOSC multiplexer. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON<7>) is set. Otherwise, code execution continues or resumes without branching (see Section 11.0 "Interrupts"). A fixed delay of interval TCSD following the wake event is required when leaving Sleep and Idle modes. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.
4.5.2
EXIT BY WDT TIME-OUT
A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 4.2 "Run Modes" and Section 4.3 "Sleep Mode"). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 20.2 "Watchdog Timer (WDT)"). The WDT timer and postscaler are cleared by executing a SLEEP or CLRWDT instruction, the loss of a currently selected clock source (if the Fail-Safe Clock Monitor is enabled) and modifying the IRCF bits in the OSCCON register if the internal oscillator block is the device clock source.
4.5.3
EXIT BY RESET
Normally, the device is held in Reset by the Oscillator Start-up Timer (OST) until the primary clock becomes ready. At that time, the OSTS bit is set and the device begins executing code. If the internal oscillator block is the new clock source, the IOFS bit is set instead. The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator if the new clock source is the primary clock. Exit delays are summarized in Table 4-2. Code execution can begin before the primary clock becomes ready. If either the Two-Speed Start-up (see Section 20.3 "Two-Speed Start-up") or Fail-Safe Clock Monitor (see Section 20.4 "Fail-Safe Clock Monitor") is enabled, the device may begin execution as soon as the Reset source has cleared. Execution is clocked by the INTOSC multiplexer driven by the internal oscillator block. Execution is clocked by the internal oscillator block until either the primary clock becomes ready or a power-managed mode is entered before the primary clock becomes ready; the primary clock is then shut down.
4.5
Exiting Idle and Sleep Modes
An exit from Sleep mode or any of the Idle modes is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 4.2 "Run Modes", Section 4.3 "Sleep Mode" and Section 4.4 "Idle Modes").
4.5.1
EXIT BY INTERRUPT
Any of the available interrupt sources can cause the device to exit from an Idle mode or the Sleep mode to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set.
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4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY
Certain exits from power-managed modes do not invoke the OST at all. There are two cases: * PRI_IDLE mode, where the primary clock source is not stopped; and * the primary clock source is not any of the LP, XT, HS or HSPLL modes. In these instances, the primary clock source either does not require an oscillator start-up delay since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (RC, EC and INTIO Oscillator modes). However, a fixed delay of interval TCSD following the wake event is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay.
TABLE 4-2:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES)
Clock Source after Wake-up LP, XT, HS HSPLL EC, RC INTOSC(2) LP, XT, HS TOST(3) TOST + trc(3) TCSD(1) TIOBST(4) TOST(4) TOST + trc(3) TCSD(1) None TOST
(3)
Clock Source before Wake-up
Exit Delay
Clock Ready Status Bit (OSCCON) OSTS IOFS OSTS IOFS OSTS IOFS OSTS IOFS
Primary Device Clock (PRI_IDLE mode)
TCSD(1)
T1OSC
HSPLL EC, RC INTOSC(1) LP, XT, HS HSPLL EC, RC INTOSC(1) LP, XT, HS
INTOSC(3)
None (Sleep mode) Note 1: 2: 3: 4:
HSPLL EC, RC INTOSC(1)
TOST + trc(3) TCSD(1) TIOBST(4)
TCSD (parameter 38) is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other required delays (see Section 4.4 "Idle Modes"). On Reset, INTOSC defaults to 1 MHz. Includes both the INTOSC 8 MHz source and postscaler derived frequencies. TOST is the Oscillator Start-up Timer (parameter 32). trc is the PLL Lock-out Timer (parameter F12); it is also designated as TPLL. Execution continues during TIOBST (parameter 39), the INTOSC stabilization period.
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5.0 RESET
The PIC18F1230/1330 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1.
5.1
RCON Register
Device Reset events are tracked through the RCON register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be cleared by the event and must be set by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 5.6 "Reset State of Registers". The RCON register also has control bits for setting interrupt priority (IPEN) and software control of the BOR (SBOREN). Interrupt priority is discussed in Section 11.0 "Interrupts". BOR is covered in Section 5.4 "Brown-out Reset (BOR)".
This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers. Stack Reset events are covered in Section 6.1.2.4 "Stack Full and Underflow Resets". WDT Resets are covered in Section 20.2 "Watchdog Timer (WDT)".
FIGURE 5-1:
RESET Instruction Stack Pointer
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
External Reset MCLR MCLRE ( )_IDLE Sleep WDT Time-out VDD Rise Detect VDD Brown-out Reset BOREN OST/PWRT OST OSC1 32 s INTRC(1) 1024 Cycles R Q 10-Bit Ripple Counter Chip_Reset S POR Pulse
PWRT
65.5 ms
11-Bit Ripple Counter
Enable PWRT Enable OST(2) Note 1: 2: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. See Table 5-2 for time-out situations.
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REGISTER 5-1:
R/W-0 IPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RCON: RESET CONTROL REGISTER
R/W-1(1) SBOREN U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0(2) POR R/W-0 BOR bit 0
IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) SBOREN: BOR Software Enable bit(1) If BOREN1:BOREN0 = 01: 1 = BOR is enabled 0 = BOR is disabled If BOREN1:BOREN0 = 00, 10 or 11: Bit is disabled and read as `0'. Unimplemented: Read as `0' RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction POR: Power-on Reset Status bit(2) 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) If SBOREN is enabled, its Reset state is `1'; otherwise, it is `0'. The actual Reset value of POR is determined by the type of device Reset. See the notes following this register and Section 5.6 "Reset State of Registers" for additional information.
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected so that subsequent Power-on Resets may be detected. 2: Brown-out Reset is said to have occurred when BOR is `0' and POR is `1' (assuming that POR was set to `1' by software immediately after a Power-on Reset).
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5.2 Master Clear (MCLR)
FIGURE 5-2:
The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. In PIC18F1230/1330 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 10.1 "PORTA, TRISA and LATA Registers" for more information.
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD
VDD D
R R1 C MCLR
PIC18FXXXX
Note 1:
5.3
Power-on Reset (POR)
2:
A Power-on Reset pulse is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 k to 10 k) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 5-2. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. Power-on Reset events are captured by the POR bit (RCON<1>). The state of the bit is set to `0' whenever a Power-on Reset occurs; it does not change for any other Reset event. POR is not reset to `1' by any hardware event. To capture multiple events, the user manually resets the bit to `1' in software following any Power-on Reset.
External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. R1 1 k will limit any current flowing into MCLR from external capacitor C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
3:
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5.4 Brown-out Reset (BOR)
PIC18F1230/1330 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV1:BORV0 and BOREN1:BOREN0 Configuration bits. There are a total of four BOR configurations which are summarized in Table 5-1. The BOR threshold is set by the BORV1:BORV0 bits. If BOR is enabled (any values of BOREN1:BOREN0 except `00'), any drop of VDD below VBOR (parameter D005) for greater than TBOR (parameter 35) will reset the device. A Reset may or may not occur if VDD falls below VBOR for less than TBOR. The chip will remain in Brown-out Reset until VDD rises above VBOR. If the Power-up Timer is enabled, it will be invoked after VDD rises above VBOR; it then will keep the chip in Reset for an additional time delay, TPWRT (parameter 33). If VDD drops below VBOR while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above VBOR, the Power-up Timer will execute the additional time delay. BOR and the Power-on Timer (PWRT) are independently configured. Enabling Brown-out Reset does not automatically enable the PWRT. change BOR configuration. It also allows the user to tailor device power consumption in software by eliminating the incremental current that the BOR consumes. While the BOR current is typically very small, it may have some impact in low-power applications. Note: Even when BOR is under software control, the Brown-out Reset voltage level is still set by the BORV1:BORV0 Configuration bits. It cannot be changed in software.
5.4.2
DETECTING BOR
When Brown-out Reset is enabled, the BOR bit always resets to `0' on any Brown-out Reset or Power-on Reset event. This makes it difficult to determine if a Brown-out Reset event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR bit is reset to `1' in software immediately after any Power-on Reset event. If BOR is `0' while POR is `1', it can be reliably assumed that a Brown-out Reset event has occurred.
5.4.3
DISABLING BOR IN SLEEP MODE
5.4.1
SOFTWARE ENABLED BOR
When BOREN1:BOREN0 = 01, the BOR can be enabled or disabled by the user in software. This is done with the control bit, SBOREN (RCON<6>). Setting SBOREN enables the BOR to function as previously described. Clearing SBOREN disables the BOR entirely. The SBOREN bit operates only in this mode; otherwise it is read as `0'. Placing the BOR under software control gives the user the additional flexibility of tailoring the application to its environment without having to reprogram the device to
When BOREN1:BOREN0 = 10, the BOR remains under hardware control and operates as previously described. Whenever the device enters Sleep mode, however, the BOR is automatically disabled. When the device returns to any other operating mode, BOR is automatically re-enabled. This mode allows for applications to recover from brown-out situations, while actively executing code, when the device requires BOR protection the most. At the same time, it saves additional power in Sleep mode by eliminating the small incremental BOR current.
TABLE 5-1:
BOR CONFIGURATIONS
Status of SBOREN (RCON<6>) Unavailable Available Unavailable Unavailable BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits.
BOR Configuration BOREN1 0 0 1 1 BOREN0 0 1 0 1
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5.5 Device Reset Timers
5.5.3 PLL LOCK TIME-OUT
PIC18F1230/1330 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: * Power-up Timer (PWRT) * Oscillator Start-up Timer (OST) * PLL Lock Time-out With the PLL enabled in its PLL mode, the time-out sequence following a Power-on Reset is slightly different from other oscillator modes. A separate timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out.
5.5.4
1. 2.
TIME-OUT SEQUENCE
5.5.1
POWER-UP TIMER (PWRT)
On power-up, the time-out sequence is as follows: After the POR pulse has cleared, PWRT time-out is invoked (if enabled). Then, the OST is activated.
The Power-up Timer (PWRT) of PIC18F1230/1330 devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 s = 65.6 ms. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip to chip due to temperature and process variation. See DC parameter 33 for details. The PWRT is enabled by clearing the PWRTEN Configuration bit.
5.5.2
OSCILLATOR START-UP TIMER (OST)
The total time-out will vary based on oscillator configuration and the status of the PWRT. Figure 5-3, Figure 5-4, Figure 5-5, Figure 5-6 and Figure 5-7 all depict time-out sequences on power-up, with the Power-up Timer enabled and the device operating in HS Oscillator mode. Figures 5-3 through 5-6 also apply to devices operating in XT or LP modes. For devices in RC mode and with the PWRT disabled, there will be no time-out at all. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, all time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 5-5). This is useful for testing purposes or to synchronize more than one PIC18FXXXX device operating in parallel.
The Oscillator Start-up Timer (OST) provides a 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter 33). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HSPLL modes and only on Power-on Reset, or on exit from most power-managed modes.
TABLE 5-2:
TIME-OUT IN VARIOUS SITUATIONS
Power-up(2) and Brown-out Reset PWRTEN = 0 66 ms
(1)
Oscillator Configuration HSPLL HS, XT, LP EC, ECIO RC, RCIO INTIO1, INTIO2 Note 1: 2:
PWRTEN = 1
(2)
Exit from Power-Managed Mode 1024 TOSC + 2 ms(2) 1024 TOSC -- -- --
+ 1024 TOSC + 2 ms 66 ms(1) 66 66 ms(1) ms(1)
1024 TOSC + 2 ms(2) 1024 TOSC -- -- --
66 ms(1) + 1024 TOSC
66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay. 2 ms is the nominal time required for the PLL to lock.
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FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT INTERNAL RESET TOST
FIGURE 5-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD MCLR INTERNAL POR
TPWRT TOST
PWRT TIME-OUT OST TIME-OUT INTERNAL RESET
FIGURE 5-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT INTERNAL RESET
TOST
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FIGURE 5-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT)
5V VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 0V
FIGURE 5-7:
TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD)
VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL
PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer.
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5.6 Reset State of Registers
Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a "Reset state" depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 5-3. These bits are used in software to determine the nature of the Reset. Table 5-4 describes the Reset states for all of the Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups.
TABLE 5-3:
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER
Program Counter 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h PC + 2 RCON Register SBOREN 1 u(2) u(2) u(2) u(2) u(2) u(2) u(2) u
(2)
STKPTR Register POR BOR STKFUL 0 u u u u u u u u u u 0 u 0 u u u u u u u u 0 u u u u u u 1 u u u STKUNF 0 u u u u u u u 1 1 u
Condition Power-on Reset RESET Instruction Brown-out Reset MCLR during Power-Managed Run Modes MCLR during Power-Managed Idle Modes and Sleep Mode WDT Time-out during Full Power or Power-Managed Run Mode MCLR during Full Power Execution Stack Full Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) Stack Underflow Error (not an actual Reset, STVREN = 0) WDT Time-out during Power-Managed Idle or Sleep Modes Interrupt Exit from Power-Managed Modes
RI 1 0 1 u u u u u u u u
TO 1 u 1 1 1 0 u u u u 0
PD 1 u 1 u 0 u u u u u 0
u(2) u(2)
PC + 2(1)
u(2)
u
u
0
u
u
u
u
Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt vector (008h or 0018h). 2: Reset state is `1' for POR and unchanged for all other Resets when software BOR is enabled (BOREN1:BOREN0 Configuration bits = 01 and SBOREN = 1); otherwise, the Reset state is `0'.
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TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Applicable Devices 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 Power-on Reset, Brown-out Reset ---0 0000 0000 0000 0000 0000 00-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 000x 1111 1111 1100 0000 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx ---- 0000 MCLR Resets, WDT Reset, RESET Instruction, Stack Resets ---0 0000 0000 0000 0000 0000 uu-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 1111 1100 0000 N/A N/A N/A N/A N/A ---- 0000 uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- 0000 uuuu uuuu ---- 0000 Wake-up via WDT or Interrupt ---0 uuuu(3) uuuu uuuu(3) uuuu uuuu(3) uu-u uuuu(3) ---u uuuu uuuu uuuu PC + 2(2) --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(1) uuuu uuuu(1) uuuu uuuu(1) N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---- uuuu
TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as `0'. 6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
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TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 Power-on Reset, Brown-out Reset N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx ---x xxxx 0000 0000 xxxx xxxx 1111 1111 0100 q000 --00 0101 ---- ---0 0q-1 11q0 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 0--- 0000 ---0 1111 0-00 0000 01-00 0-00 0-00 0000 000- -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 000x MCLR Resets, WDT Reset, RESET Instruction, Stack Resets N/A N/A N/A N/A N/A ---- 0000 uuuu uuuu ---u uuuu 0000 0000 uuuu uuuu 1111 1111 0100 q000 --00 0101 ---- ---0 0q-q qquu uuuu uuuu uuuu uuuu u0uu uuuu uuuu uuuu uuuu uuuu 0--- 0000 ---0 1111 0-00 0000 01-00 0-00 0-00 0000 000- -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 000x Wake-up via WDT or Interrupt N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuqu --uu uuuu ---- ---u uq-u qquu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu ---u uuuu u-uu uuuu uu-uu u-uu u-uu uuuu uuu- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON LVDCON WDTCON RCON
(4)
TMR1H TMR1L T1CON ADRESH ADRESL ADCON0 ADCON1 ADCON2 BAUDCON CVRCON CMCON SPBRGH SPBRG RCREG TXREG TXSTA RCSTA
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as `0'. 6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
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TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1230 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 1330 Power-on Reset, Brown-out Reset 0000 0000 0000 0000 0000 0000 xx-0 x000 ---1 ------0 ------0 ---1--1 -1-0--0 -0-0--0 -0--111 1111 -000 0000 -000 0000 00-0 0000 0000 0000 00-- ---0000 0000 ---- 0000 1111 1111 ---- 1111 1111 1111 1111 1111(5) 0000 0000 --00 0000 0000 0000 --00 0000 0000 0000 --00 0000 0--- -000 xxxx xxxx xxxx xxxx 0000 0000
(5)
MCLR Resets, WDT Reset, RESET Instruction, Stack Resets 0000 0000 0000 0000 0000 0000 uu-0 u000 ---1 ------0 ------0 ---1--1 -1-0--0 -0-0--0 -0--111 1111 -000 0000 -000 0000 00-0 0000 uuuu uuuu 00-- ---0000 0000 ---- 0000 1111 1111 ---- 1111 1111 1111 1111 1111(5) 0000 0000 --00 0000 0000 0000 --00 0000 0000 0000 --00 0000 0--- -000 uuuu uuuu uuuu uuuu(5) 0000 0000
Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu 0000 0000 uu-0 u000 ---u ------u ------u ---u--u -u-u--u -u--(1) u--u -u--uuu uuuu -uuu uuuu(1) -uuu uuuu uu-u uuuu uuuu uuuu uu-- ---uuuu uuuu ---- uuuu uuuu uuuu ---- uuuu uuuu uuuu uuuu uuuu(5) uuuu uuuu --uu uuuu uuuu uuuu --uu uuuu uuuu uuuu --uu uuuu u--- -uuu uuuu uuuu uuuu uuuu(5) uuuu uuuu
EEADR EEDATA EECON2 EECON1 IPR3 PIR3 PIE3 IPIR2 PIR2 PIE2 IPR1 PIR1 PIE1 OSCTUNE PTCON0 PTCON1 PTMRL PTMRH PTPERL PTPERH TRISB TRISA PDC0L PDC0H PDC1L PDC1H PDC2L PDC2H FLTCONFIG LATB LATA SEVTCMPL
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as `0'. 6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
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TABLE 5-4:
Register
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Applicable Devices 1230 1230 1230 1230 1230 1230 1230 1230 1330 1330 1330 1330 1330 1330 1330 1330 Power-on Reset, Brown-out Reset ---- 0000 -100 -000(6) -000 -000(6) 0000 0-00 0000 0000 --11 1111 --00 0000 xxxx xxxx xx0x xxxx
(5)
MCLR Resets, WDT Reset, RESET Instruction, Stack Resets ---- 0000 -100 -000(6) -000 -000(6) 0000 0-00 0000 0000 --11 1111 --00 0000 uuuu uuuu uu0u uuuu(5)
Wake-up via WDT or Interrupt ---- uuuu -uuu -uuu(6) -uuu -uuu(6) uuuu u-uu uuuu uuuu --uu uuuu --uu uuuu uuuu uuuu uuuu uuuu(5)
SEVTCMPH PWMCON0 PWMCON1 DTCON OVDCOND OVDCONS PORTB PORTA
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 5-3 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read as `0'. 6: Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
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6.0 MEMORY ORGANIZATION
6.1 Program Memory Organization
There are three types of memory in PIC18 Enhanced microcontroller devices: * Program Memory * Data RAM * Data EEPROM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers. Additional detailed information on the operation of the Flash program memory is provided in Section 7.0 "Flash Program Memory". Data EEPROM is discussed separately in Section 8.0 "Data EEPROM Memory". PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all `0's (a NOP instruction). The PIC18F1230 has 4 Kbytes of Flash memory and can store up to 2,048 single-word instructions. The PIC18F1330 has 8 Kbytes of Flash memory and can store up to 4,096 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. The program memory maps for PIC18F1230 and PIC18F1330 devices are shown in Figure 6-1.
FIGURE 6-1:
PROGRAM MEMORY MAP AND STACK FOR PIC18F1230/1330 DEVICES
PIC18F1230 PIC18F1330
PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1

PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1

Stack Level 31 Reset Vector 0000h
Stack Level 31 Reset Vector 0000h
High-Priority Interrupt Vector 0008h Low-Priority Interrupt Vector 0018h On-Chip Program Memory 0FFFh 1000h
High-Priority Interrupt Vector 0008h Low-Priority Interrupt Vector 0018h
On-Chip Program Memory User Memory Space User Memory Space
1FFFh 2000h
Read `0'
Read `0'
1FFFFFh 200000h
1FFFFFh 200000h
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6.1.1 PROGRAM COUNTER
The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes to the PCL. Similarly, the upper two bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads the PCL. This is useful for computed offsets to the PC (see Section 6.1.4.1 "Computed GOTO"). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit of PCL is fixed to a value of `0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-ofStack Special Function Registers. Data can also be pushed to, or popped from the stack, using these registers. A CALL type instruction causes a push onto the stack; the Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack; the contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to `00000' after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of `00000'; this is only a Reset value. Status bits indicate if the stack is full, has overflowed or has underflowed.
6.1.2.1
Top-of-Stack Access
6.1.2
RETURN ADDRESS STACK
The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions.
Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, hold the contents of the stack location pointed to by the STKPTR register (Figure 6-2). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user-defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption.
FIGURE 6-2:
RETURN ADDRESS STACK AND ASSOCIATED REGISTERS
Return Address Stack <20:0> 11111 11110 11101
Top-of-Stack Registers TOSU 00h TOSH 1Ah TOSL 34h Top-of-Stack 001A34h 000D58h
Stack Pointer STKPTR<4:0> 00010
00011 00010 00001 00000
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6.1.2.2 Return Stack Pointer (STKPTR)
The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (Stack Overflow Reset Enable) Configuration bit. (Refer to Section 20.1 "Configuration Bits" for a description of the device Configuration bits.) If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected.
6.1.2.3
PUSH and POP Instructions
Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execution, is a desirable feature. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value.
REGISTER 6-1:
R/C-0 STKFUL(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7
STKPTR: STACK POINTER REGISTER
R/C-0 U-0 -- R/W-0 SP4 R/W-0 SP3 R/W-0 SP2 R/W-0 SP1 R/W-0 SP0 bit 0 C = Clearable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
STKUNF(1)
STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur Unimplemented: Read as `0' SP4:SP0: Stack Pointer Location bits Bit 7 and bit 6 are cleared by user software or by a POR.
bit 6
bit 5 bit 4-0 Note 1:
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6.1.2.4 Stack Full and Underflow Resets 6.1.4
Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKFUL or STKUNF bit but not cause a device Reset. The STKFUL or STKUNF bit is cleared by the user software or a Power-on Reset.
LOOK-UP TABLES IN PROGRAM MEMORY
There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: * Computed GOTO * Table Reads
6.1.4.1
Computed GOTO
6.1.3
FAST REGISTER STACK
A Fast Register Stack is provided for the STATUS, WREG and BSR registers, to provide a "fast return" option for interrupts. The stack for each register is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources will push values into the Stack registers. The values in the registers are then loaded back into their associated registers if the RETFIE, FAST instruction is used to return from the interrupt. If both low and high-priority interrupts are enabled, the Stack registers cannot be used reliably to return from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the Stack register values stored by the low-priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the Fast Register Stack for returns from interrupt. If no interrupts are used, the Fast Register Stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the Fast Register Stack. Example 6-1 shows a source code example that uses the Fast Register Stack during a subroutine call and return.
A computed GOTO is accomplished by adding an offset to the program counter. An example is shown in Example 6-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW nn instructions that returns the value `nn' to the calling function. The offset value (in WREG) specifies the number of bytes that the program counter should advance and should be multiples of 2 (LSb = 0). In this method, only one data byte may be stored in each instruction location and room on the return address stack is required.
EXAMPLE 6-2:
MOVF CALL nn00h ADDWF RETLW RETLW RETLW . . .
COMPUTED GOTO USING AN OFFSET VALUE
OFFSET, W TABLE PCL nnh nnh nnh
ORG TABLE
6.1.4.2
Table Reads and Table Writes
EXAMPLE 6-1:
CALL SUB1, FAST
FAST REGISTER STACK CODE EXAMPLE
;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK
A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes. The Table Pointer (TBLPTR) register specifies the byte address and the Table Latch (TABLAT) register contains the data that is read from or written to program memory. Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 7.1 "Table Reads and Table Writes".
SUB1 RETURN, FAST
;RESTORE VALUES SAVED ;IN FAST REGISTER STACK
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6.2
6.2.1
PIC18 Instruction Cycle
CLOCKING SCHEME
6.2.2
INSTRUCTION FLOW/PIPELINING
The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 6-3.
An "Instruction Cycle" consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 6-3). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 6-3:
OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC mode)
CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Internal Phase Clock
PC PC + 2 PC + 4
Execute INST (PC - 2) Fetch INST (PC)
Execute INST (PC) Fetch INST (PC + 2)
Execute INST (PC + 2) Fetch INST (PC + 4)
EXAMPLE 6-3:
INSTRUCTION PIPELINE FLOW
TCY0 TCY1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 TCY2 TCY3 TCY4 TCY5
1. MOVLW 55h 2. MOVWF PORTB 3. BRA 4. BSF SUB_1
Fetch 1
PORTA, BIT3 (Forced NOP)
5. Instruction @ address SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed.
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6.2.3 INSTRUCTIONS IN PROGRAM MEMORY
The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read `0' (see Section 6.1.1 "Program Counter"). Figure 6-4 shows an example of how instruction words are stored in the program memory. The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 6-4 shows how the instruction, GOTO 0006h, is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 22.0 "Instruction Set Summary" provides further details of the instruction set.
FIGURE 6-4:
INSTRUCTIONS IN PROGRAM MEMORY
LSB = 1 Program Memory Byte Locations LSB = 0 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h
Instruction 1: Instruction 2: Instruction 3:
MOVLW GOTO MOVFF
055h 0006h 123h, 456h
0Fh EFh F0h C1h F4h
55h 03h 00h 23h 56h
6.2.4
TWO-WORD INSTRUCTIONS
The standard PIC18 instruction set has four two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instructions always has `1111' as its four Most Significant bits; the other 12 bits are literal data, usually a data memory address. The use of `1111' in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence - immediately after the first word - the data in the second word is accessed
and used by the instruction sequence. If the first word is skipped for some reason and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 6-4 shows how this works. Note: See Section 6.6 "PIC18 Instruction Execution and the Extended Instruction Set" for information on two-word instructions in the extended instruction set.
EXAMPLE 6-4:
CASE 1: Object Code 0110 0110 0000 1100 0001 0010 1111 0100 0101 0010 0100 0000 CASE 2: Object Code 0110 1100 1111 0010 0110 0001 0100 0100 0000 0010 0101 0000
TWO-WORD INSTRUCTIONS
Source Code 0000 0011 0110 0000 TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? REG1, REG2 ; No, skip this word ; Execute this word as a NOP REG3 ; continue code
Source Code 0000 0011 0110 0000 TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code
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6.3
Note:
Data Memory Organization
The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.5 "Data Memory and the Extended Instruction Set" for more information.
6.3.1
BANK SELECT REGISTER (BSR)
The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each; PIC18F1230/ 1330 devices implement 1 bank. Figure 6-5 shows the data memory organization for the PIC18F1230/1330 devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user's application. Any read of an unimplemented location will read as `0's. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this subsection. To ensure that commonly used registers (SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 6.3.2 "Access Bank" provides a detailed description of the Access RAM.
Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the four Most Significant bits of a location's address; the instruction itself includes the eight Least Significant bits. Only the four lower bits of the BSR are implemented (BSR3:BSR0). The upper four bits are unused; they will always read `0' and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory. The 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank's lower boundary. The relationship between the BSR's value and the bank division in data memory is shown in Figure 6-6. Since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h, while the BSR is 0Fh, will end up resetting the program counter. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return `0's. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure 6-5 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers.
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FIGURE 6-5:
BSR<3:0> = 0000 00h Bank 0 FFh
DATA MEMORY MAP FOR PIC18F1230/1330 DEVICES
Data Memory Map Access RAM GPR 000h 07Fh 080h 0FFh When a = 0: The BSR is ignored and the Access Bank is used. The first 128 bytes are general purpose RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When a = 1: The BSR specifies the Bank used by the instruction.
Access Bank = 0001 Bank 1 to Bank 14
Unused Read `00h'
= 1110
7Fh Access RAM High 80h (SFRs) FFh
Access RAM Low
00h
= 1111
00h Bank 15 FFh
Unused Read `00h'
SFR
EFFh F00h F7Fh F80h FFFh
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FIGURE 6-6:
7
USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING)
BSR(1) 0
0
0
0
0
0
0
0
0
000h 100h
Data Memory
Bank 0 00h FFh 00h
7
From Opcode(2)
0
1
1
1
1
1
1
1
1
Bank Select(2)
Bank 1 through Bank 13
E00h Bank 14 F00h FFFh Note 1: 2: Bank 15
FFh 00h FFh 00h FFh
The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction.
6.3.2
ACCESS BANK
While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 128 bytes of memory (00h-7Fh) in Bank 0 and the last 128 bytes of memory (80h-FFh) in Block 15. The lower half is known as the "Access RAM" and is composed of GPRs. The upper half is where the device's SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 6-5). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the `a' parameter in the instruction). When `a' is equal to `1', the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When `a' is `0',
however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. Using this "forced" addressing allows the instruction to operate on a data address in a single cycle without updating the BSR first. For 8-bit addresses of 80h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 80h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 6.5.3 "Mapping the Access Bank in Indexed Literal Offset Addressing Mode".
6.3.3
GENERAL PURPOSE REGISTER FILE
PIC18 devices may have banked memory in the GPR area. This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets.
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6.3.4 SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy the top half of Bank 15 (F80h to FFFh). A list of these registers is given in Table 6-1 and Table 6-2. The SFRs can be classified into two sets: those associated with the "core" device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and Interrupt registers are described in their respective chapters, while the ALU's STATUS register is described later in this section. Registers related to the operation of a peripheral feature are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as `0's.
TABLE 6-1:
Address FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh FEEh FECh FEBh FEAh FE9h FE8h FE7h FE5h FE4h FE3h FE2h FE1h FE0h Note 1: 2:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F1230/1330 DEVICES
Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0(1) POSTINC0(1) PREINC0 FSR0H FSR0L WREG INDF1(1) POSTDEC1(1) PREINC1 FSR1H FSR1L BSR
(1) (1)
Address FDFh FDEh FDCh FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC7h FC6h FC5h FC4h FC3h FC2h FC1h FC0h
Name INDF2(1) POSTINC2(1) PREINC2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON --(2) OSCCON LVDCON WDTCON RCON TMR1H TMR1L T1CON --
(2) (1)
Address FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FB1h FB0h FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h
Name --
(2)
Address F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h F85h F84h F83h F82h F81h F80h
Name IPR1 PIR1 PIE1 --(2) OSCTUNE PTCON0 PTCON1 PTMRL PTMRH PTPERL PTPERH --(2) TRISB TRISA PDC0L PDC0H PDC1L PDC1H PDC2L PDC2H FLTCONFIG LATB LATA SEVTCMPL SEVTCMPH PWMCON0 PWMCON1 DTCON OVDCOND OVDCONS PORTB PORTA
--(2) --(2) --(2) --(2) --(2) --(2) BAUDCON --(2) --(2) CVRCON CMCON --(2) --(2) --(2) SPBRGH SPBRG RCREG TXREG TXSTA RCSTA --(2) EEADR EEDATA EECON2(1) EECON1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2
FDDh POSTDEC2(1) PLUSW2(1)
FEDh POSTDEC0(1) PLUSW0(1)
--(2) --(2) --(2) --
(2)
--(2) --(2) --(2) ADRESH ADRESL ADCON0 ADCON1 ADCON2
FE6h POSTINC1(1)
PLUSW1(1)
This is not a physical register. Unimplemented registers are read as `0'.
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TABLE 6-2:
File Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L
REGISTER FILE SUMMARY (PIC18F1230/1330)
Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR ---0 0000 0000 0000 0000 0000 SP4 SP3 SP2 SP1 SP0 00-0 0000 ---0 0000 0000 0000 0000 0000 bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR0IE INTEDG1 INT3IE INT0IE INTEDG2 INT2IE RBIE INTEDG3 INT1IE TMR0IF TMR0IP INT3IF INT0IF INT3IP INT2IF RBIF RBIP INT1IF 0000 000x 1111 1111 1100 0000 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx Bank Select Register ---- 0000 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx Holding Register for PC<20:16> Details on Page: 47, 52 47, 52 47, 52 47, 53 47, 52 47, 52 47, 52 47, 74 47, 74 47, 74 47, 74 47, 85 47, 85 47, 95 47, 96 47, 97 47, 66 47, 66 47, 66 47, 66 47, 66 47, 66 47, 66 47, 54 47, 66 47, 66 47, 66 47, 66 47, 66 47, 66 47, 66 47, 57 48, 66 48, 66 48, 66 48, 66 48, 66 48, 66 48, 66
Top-of-Stack Upper Byte (TOS<20:16>)
Top-of-Stack High Byte (TOS<15:8>) Top-of-Stack Low Byte (TOS<7:0>) STKFUL(5) -- STKUNF(5) -- -- --
Holding Register for PC<15:8> PC Low Byte (PC<7:0>) -- -- Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch Product Register High Byte Product Register Low Byte GIE/GIEH RBPU INT2IP PEIE/GIEL INTEDG0 INT1IP
Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value of FSR0 offset by W -- Working Register Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value of FSR1 offset by W -- -- -- -- -- -- -- -- Indirect Data Memory Address Pointer 1 High Byte Indirect Data Memory Address Pointer 1 Low Byte Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value of FSR2 offset by W -- -- -- -- Indirect Data Memory Address Pointer 2 High Byte Indirect Data Memory Address Pointer 2 Low Byte -- -- -- Indirect Data Memory Address Pointer 0 High Byte Indirect Data Memory Address Pointer 0 Low Byte
Legend: Note 1: 2: 3: 4: 5: 6: 7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as `0'. See Section 5.4 "Brown-out Reset (BOR)". The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 3.6.4 "PLL in INTOSC Modes". The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as `0'. This bit is read-only. RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. Bit 7 and bit 6 are cleared by user software or by a POR. Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. This bit has no effect if the Configuration bit, WDTEN, is enabled.
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TABLE 6-2:
File Name STATUS TMR0H TMR0L T0CON OSCCON LVDCON WDTCON RCON TMR1H TMR1L T1CON ADRESH ADRESL ADCON0 ADCON1 ADCON2 BAUDCON CVRCON CMCON SPBRGH SPBRG RCREG TXREG TXSTA RCSTA EEADR EEDATA EECON2 EECON1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 OSCTUNE PTCON0 PTCON1
REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED)
Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 N Bit 3 OV Bit 2 Z Bit 1 DC Bit 0 C Value on POR, BOR ---x xxxx 0000 0000 xxxx xxxx T0CS IRCF1 IRVST --
(1)
Details on Page: 48, 64 48, 109 48, 109 48, 107 48, 28 48, 187 48, 203 48, 40 48, 115 48, 115 48, 111 48, 178 48, 178 48, 169 48, 170 48, 171 48, 150 48, 184 48, 179 48, 152 48, 152 48, 160 48, 157 48, 148 48, 149 49, 81 49, 81 49, 72 48, 73 49, 103 49, 99 49, 101 49, 103 49, 99 49, 101 49, 102 49, 98 49, 100 49, 25 49, 122 49, 122
Timer0 Register High Byte Timer0 Register Low Byte TMR0ON IDLEN -- -- IPEN T016BIT IRCF2 -- -- SBOREN T0SE IRCF0 LVDEN -- RI PSA OSTS LVDL3 -- TO T0PS2 IOFS LVDL2 -- PD T0PS1 SCS1 LVDL1 -- POR T0PS0 SCS0 LVDL0 SWDTEN(7) BOR
1111 1111 0100 q000 --00 0101 ---- ---0 0q-1 11q0 xxxx xxxx xxxx xxxx
--
Timer1 Register High Byte Timer1 Register Low Byte RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON A/D Result Register High Byte A/D Result Register Low Byte SEVTEN -- ADFM ABDOVF CVREN C2OUT -- -- -- RCIDL -- C1OUT -- -- ACQT2 RXDTP CVRR C0OUT -- VCFG0 ACQT1 TXCKP CVRSS -- CHS1 PCFG3 ACQT0 BRG16 CVR3 -- CHS0 PCFG2 ADCS2 -- CVR2 CMEN2 GO/DONE PCFG1 ADCS1 WUE CVR1 CMEN1 ADON PCFG0 ADCS0 ABDEN CVR0 CMEN0
0000 0000 xxxx xxxx xxxx xxxx 0--- 0000 ---0 1111 0-00 0000 01-0 00-00 0-00 0000 000- -000 0000 0000 0000 0000 0000 0000 0000 0000
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte EUSART Receive Register EUSART Transmit Register CSRC SPEN TX9 RX9 TXEN SREN SYNC CREN SENDB ADDEN BRGH FERR TRMT OERR TX9D RX9D
0000 0010 0000 000x 0000 0000 0000 0000 0000 0000
EEPROM Address Register EEPROM Data Register EEPROM Control Register 2 (not a physical register) EEPGD -- -- -- OSCFIP OSCFIF OSCFIE -- -- -- INTSRC PTOPS3 PTEN CFGS -- -- -- -- -- -- ADIP ADIF ADIE PLLEN(2) PTOPS2 PTDIR -- -- -- -- -- -- -- RCIP RCIF RCIE -- PTOPS1 -- FREE PTIP PTIF PTIE EEIP EEIF EEIE TXIP TXIF TXIE TUN4 PTOPS0 -- WRERR -- -- -- -- -- -- CMP2IP CMP2IF CMP2IE TUN3 PTCKPS1 -- WREN -- -- -- LVDIP LVDIF LVDIE CMP1IP CMP1IF CMP1IE TUN2 PTCKPS0 -- WR -- -- -- -- -- -- CMP0IP CMP0IF CMP0IE TUN1 PTMOD1 -- RD -- -- -- -- -- -- TMR1IP TMR1IF TMR1IE TUN0 PTMOD0 --
xx-0 x000 ---1 ------0 ------0 ---1--1 -1-0--0 -0-0--0 -0--111 1111 -000 0000 -000 0000 00-0 0000 0000 0000 00-- ----
Legend: Note 1: 2: 3: 4: 5: 6: 7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as `0'. See Section 5.4 "Brown-out Reset (BOR)". The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 3.6.4 "PLL in INTOSC Modes". The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as `0'. This bit is read-only. RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. Bit 7 and bit 6 are cleared by user software or by a POR. Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. This bit has no effect if the Configuration bit, WDTEN, is enabled.
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TABLE 6-2:
File Name PTMRL PTMRH PTPERL PTPERH TRISB TRISA PDC0L PDC0H PDC1L PDC1H PDC2L PDC2H FLTCONFIG LATB LATA SEVTCMPL SEVTCMPH PWMCON0 PWMCON1 DTCON OVDCOND OVDCONS PORTB PORTA
REGISTER FILE SUMMARY (PIC18F1230/1330) (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 0000 0000 -- -- PWM Time Base Register (upper 4 bits) PWM Time Base Period Register (upper 4 bits) ---- 0000 1111 1111 ---- 1111 1111 1111 1111 1111 0000 0000 --00 0000 0000 0000 --00 0000 0000 0000 --00 0000 FLTAS FLTAMOD FLTAEN 0--- -000 xxxx xxxx xxxx xxxx 0000 0000 PWM Special Event Compare Register (upper 4 bits) -- SEVTDIR DT3 POVD3 POUT3 RB3 RA3 PMOD2 -- DT2 POVD2 POUT2 RB2 RA2 PMOD1 UDIS DT1 POVD1 POUT1 RB1 RA1 PMOD0 OSYNC DT0 POVD0 POUT0 RB0 RA0 ---- 0000 -100 -000 -000 -000 SEVOPS3 DTPS1 -- -- RB7 RA7(4) SEVOPS2 DTPS0 -- -- RB6 RA6(4) SEVOPS1 DT5 POVD5 POUT5 RB5 RA5(3) SEVOPS0 DT4 POVD4 POUT4 RB4 RA4 0000 0-00 0000 0000 --11 1111 --00 0000 xxxx xxxx xx0x xxxx 50, 124 50, 136 50, 140 50, 140 50, 90 50, 87 -- -- Details on Page: 49, 125 49, 125 49, 125 49, 125 49, 90 49, 87 49, 131 49, 131 49, 131 49, 131 49, 131 49, 131 49, 143 49, 90 49, 87 49, 144 50, 144 50, 123
PWM Time Base Register (lower 8 bits) -- -- TRISA7(4) -- -- -- BRFEN LATA7(4) -- -- -- -- TRISA6(4) -- -- -- -- LATA6(4) -- -- -- PWM Time Base Period Register (lower 8 bits) PORTB Data Direction Control Register PORTA Data Direction Control Register PWM Duty Cycle #0H Register (upper 6 bits) PWM Duty Cycle #1H Register (upper 6 bits) PWM Duty Cycle #2H Register (upper 6 bits) -- PWM Duty Cycle #0L Register (lower 8 bits) PWM Duty Cycle #1L Register (lower 8 bits) PWM Duty Cycle #2L Register (lower 8 bits)
PORTB Output Latch Register (Read and Write to Data Latch) PORTA Output Latch Register (Read and Write to Data Latch) -- -- PWM Special Event Compare Register (lower 8 bits) PWMEN2(6) PWMEN1(6) PWMEN0(6)
Legend: Note 1: 2: 3: 4: 5: 6: 7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as `0'. See Section 5.4 "Brown-out Reset (BOR)". The PLLEN bit is only available in specific oscillator configurations; otherwise, it is disabled and reads as `0'. See Section 3.6.4 "PLL in INTOSC Modes". The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as `0'. This bit is read-only. RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. Bit 7 and bit 6 are cleared by user software or by a POR. Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L. This bit has no effect if the Configuration bit, WDTEN, is enabled.
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6.3.5 STATUS REGISTER
The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed. Therefore, the result of an instruction with the STATUS register as its destination may be different than intended. As an example, CLRF STATUS will set the Z bit and leave the remaining Status bits unchanged (`000u u1uu'). It is recommended that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions that do not affect Status bits, see the instruction set summaries in Table 22-2 and Table 22-3. Note: The C and DC bits operate as the borrow and digit borrow bits, respectively, in subtraction.
REGISTER 6-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4
STATUS REGISTER
U-0 -- U-0 -- R/W-x N R/W-x OV R/W-x Z R/W-x DC(1) R/W-x C(2) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result C: Carry/borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. For borrow, the polarity is reversed. A subtraction is executed by adding the 2's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register.
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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6.4
Note:
Data Addressing Modes
The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.5 "Data Memory and the Extended Instruction Set" for more information.
The Access RAM bit `a' determines how the address is interpreted. When `a' is `1', the contents of the BSR (Section 6.3.1 "Bank Select Register (BSR)") are used with the address to determine the complete 12-bit address of the register. When `a' is `0', the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation's results is determined by the destination bit `d'. When `d' is `1', the results are stored back in the source register, overwriting its original contents. When `d' is `0', the results are stored in the W register. Instructions without the `d' argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register.
The data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: * * * * Inherent Literal Direct Indirect
An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in greater detail in Section 6.5.1 "Indexed Addressing with Literal Offset".
6.4.3
INDIRECT ADDRESSING
6.4.1
INHERENT AND LITERAL ADDRESSING
Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way but require an additional explicit argument in the opcode. This is known as Literal Addressing mode because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address.
Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as Special Function Registers, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures, such as tables and arrays in data memory. The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code, using loops, such as the example of clearing an entire RAM bank in Example 6-5.
EXAMPLE 6-5:
HOW TO CLEAR RAM (BANK 0) USING INDIRECT ADDRESSING
FSR0, 00h POSTINC0 ; ; ; ; ; ; ; ; Clear INDF register then inc pointer All done with Bank0? NO, clear next YES, continue
6.4.2
DIRECT ADDRESSING
NEXT
Direct Addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byteoriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their Least Significant Byte. This address specifies either a register address in one of the banks of data RAM (Section 6.3.3 "General Purpose Register File") or a location in the Access Bank (Section 6.3.2 "Access Bank") as the data source for the instruction.
LFSR CLRF
BTFSS BRA CONTINUE
FSR0H, 0 NEXT
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6.4.3.1 FSR Registers and the INDF Operand 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW
At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Indirect Addressing is accomplished with a set of Indirect File Operands, INDF0 through INDF2. These can be thought of as "virtual" registers: they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction's target. The INDF operand is just a convenient way of using the pointer. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are "virtual" registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value. They are: * POSTDEC: accesses the FSR value, then automatically decrements it by 1 afterwards * POSTINC: accesses the FSR value, then automatically increments it by 1 afterwards * PREINC: increments the FSR value by 1, then uses it in the operation * PLUSW: adds the signed value of the W register (range of -127 to 128) to that of the FSR and uses the new value in the operation. In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value offset by that in the W register; neither value is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers. Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.).
FIGURE 6-7:
INDIRECT ADDRESSING
000h Bank 0 100h 200h Bank 1 Bank 2
Using an instruction with one of the indirect addressing registers as the operand....
ADDWF, INDF1, 1
...uses the 12-bit address stored in the FSR pair associated with that register....
FSR1H:FSR1L 7 0 7 0
300h
xxxx1110
11001100
Bank 3 through Bank 13
...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. E00h Bank 14 F00h FFFh Bank 15
Data Memory
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The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory.
6.5.1
INDEXED ADDRESSING WITH LITERAL OFFSET
6.4.3.3
Operations by FSRs on FSRs
Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1 using INDF0 as an operand will return 00h. Attempts to write to INDF1 using INDF0 as the operand will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses Indirect Addressing. Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device.
Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair within Access RAM. Under the proper conditions, instructions that use the Access Bank - that is, most bit-oriented and byte-oriented instructions - can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. When using the extended instruction set, this addressing mode requires the following: * The use of the Access Bank is forced (`a' = 0); and * The file address argument is less than or equal to 5Fh. Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing), or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer, specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation.
6.5.2
INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE
6.5
Data Memory and the Extended Instruction Set
Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte-oriented and bit-oriented instructions, or almost one-half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte-oriented and bit-oriented instructions are not affected if they do not use the Access Bank (Access RAM bit is `1'), or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled is shown in Figure 6-8. Those who desire to use bit-oriented or byte-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 22.2.1 "Extended Instruction Syntax".
Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different; this is due to the introduction of a new addressing mode for the data memory space. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged.
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FIGURE 6-8: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED)
EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff)
When `a' = 0 and f 60h: The instruction executes in Direct Forced mode. `f' is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations 060h to 07Fh (Bank 0) and F80h to FFFh (Bank 15) of data memory. Locations below 60h are not available in this addressing mode.
000h 060h 080h 100h Bank 1 through Bank 14 00h 60h 80h
Bank 0
Valid range for `f'
F00h Bank 15 F80h SFRs FFFh Data Memory
Access RAM
FFh
When `a' = 0 and f5Fh: The instruction executes in Indexed Literal Offset mode. `f' is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. Note that in this mode, the correct syntax is now: ADDWF [k], d where `k' is the same as `f'.
000h Bank 0 080h 100h Bank 1 through Bank 14 FSR2H F00h Bank 15 F80h SFRs FFFh Data Memory FSR2L 001001da ffffffff
When `a' = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). `f' is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space.
000h Bank 0 080h 100h Bank 1 through Bank 14
BSR 00000000
001001da ffffffff
F00h Bank 15 F80h SFRs FFFh Data Memory
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6.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET ADDRESSING MODE
Remapping of the Access Bank applies only to operations using the Indexed Literal Offset Addressing mode. Operations that use the BSR (Access RAM bit is `1') will continue to use Direct Addressing as before.
The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom half of Bank 0, this mode maps the contents from Bank 0 and a user-defined "window" that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 6.3.2 "Access Bank"). An example of Access Bank remapping in this addressing mode is shown in Figure 6-9.
6.6
PIC18 Instruction Execution and the Extended Instruction Set
Enabling the extended instruction set adds eight additional commands to the existing PIC18 instruction set. These instructions are executed as described in Section 22.2 "Extended Instruction Set".
FIGURE 6-9:
Example Situation:
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING MODE
000h 05Fh 07Fh 090h 0EFh 100h Bank 0
ADDWF f, d, a FSR2H:FSR2L = 090h Locations in the region from the FSR2 Pointer (090h) to the pointer plus 05Fh (0EFh) are mapped to the bottom of the Access RAM (000h-05Fh). Locations in Bank 0 from 060h to 07Fh are mapped, as usual, to the middle of the Access Bank. Special Function Registers at F80h through FFFh are mapped to 80h through FFh, as usual. Bank 0 addresses below 5Fh can still be addressed by using the BSR.
Window Bank 0 00h Bank 0 "Window" 5Fh Bank 0 Bank 1 through Bank 14 7Fh 80h
SFRs FFh
Access Bank
F00h Bank 15 F80h FFFh SFRs
Data Memory
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7.0 FLASH PROGRAM MEMORY
7.1 Table Reads and Table Writes
The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed on one byte at a time. A write to program memory is executed on blocks of 8 bytes at a time. Program memory is erased in blocks of 64 bytes at a time. A bulk erase operation may not be issued from user code. Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: * Table Read (TBLRD) * Table Write (TBLWT) The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into the data RAM space. Figure 7-1 shows the operation of a table read with program memory and data RAM. Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 7.5 "Writing to Flash Program Memory". Figure 7-2 shows the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned.
FIGURE 7-1:
TABLE READ OPERATION
Instruction: TBLRD*
Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL
Program Memory Table Latch (8-bit) TABLAT
Program Memory (TBLPTR)
Note 1: Table Pointer register points to a byte in program memory.
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FIGURE 7-2: TABLE WRITE OPERATION
Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT
Program Memory (TBLPTR)
Note 1: Table Pointer actually points to one of 8 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 "Writing to Flash Program Memory".
7.2
Control Registers
Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: * * * * EECON1 register EECON2 register TABLAT register TBLPTR registers
The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set and cleared when the internal programming timer expires and the write operation is complete. Note: During normal operation, the WRERR may read as `1'. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly.
7.2.1
EECON1 AND EECON2 REGISTERS
The EECON1 register (Register 7-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's. The EEPGD control bit determines if the access will be a program or data EEPROM memory access. When clear, any subsequent operations will operate on the data EEPROM memory. When set, any subsequent operations will operate on the program memory. The CFGS control bit determines if the access will be to the Configuration/Calibration registers or to program memory/data EEPROM memory. When set, subsequent operations will operate on Configuration registers regardless of EEPGD (see Section 20.0 "Special Features of the CPU"). When clear, memory selection access is determined by EEPGD.
The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. Note: The EEIF interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software.
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REGISTER 7-1:
R/W-x EEPGD bit 7 Legend: R = Readable bit -n = Value at POR bit 7 S = Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EECON1: EEPROM CONTROL REGISTER 1
R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR
(1)
R/W-0 WREN
R/S-0 WR
R/S-0 RD bit 0
EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory Unimplemented: Read as `0' FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only WRERR: Flash Program/Data EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation, or an improper write attempt) 0 = The write operation completed WREN: Flash Program/Data EEPROM Write Enable bit 1 = Allows write cycles to Flash program/data EEPROM 0 = Inhibits write cycles to Flash program/data EEPROM WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read. (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.) 0 = Does not initiate an EEPROM read When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition.
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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7.2.2 TABLAT - TABLE LATCH REGISTER 7.2.4 TABLE POINTER BOUNDARIES
The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT. When the timed write to program memory begins (via the WR bit), the 19 MSbs of the TBLPTR (TBLPTR<21:3>) determine which program memory block of 8 bytes is written to. The Table Pointer register's three LSBs (TBLPTR<2:0>) are ignored. For more detail, see Section 7.5 "Writing to Flash Program Memory". When an erase of program memory is executed, the 16 MSbs of the Table Pointer register (TBLPTR<21:6>) point to the 64-byte block that will be erased. The Least Significant bits (TBLPTR<5:0>) are ignored. Figure 7-3 describes the relevant boundaries of TBLPTR based on Flash program memory operations.
7.2.3
TBLPTR - TABLE POINTER REGISTER
The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The loworder 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the device ID, the user ID and the Configuration bits. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 7-1. These operations on the TBLPTR only affect the low-order 21 bits.
TABLE 7-1:
Example TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+*
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write
FIGURE 7-3:
21
TABLE POINTER BOUNDARIES BASED ON OPERATION
TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0
TABLE ERASE TBLPTR<21:6> TABLE WRITE TBLPTR<21:3> TABLE READ - TBLPTR<21:0>
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7.3 Reading the Flash Program Memory
The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 7-4 shows the interface between the internal program memory and the TABLAT.
FIGURE 7-4:
READS FROM FLASH PROGRAM MEMORY
Program Memory
(Even Byte Address)
(Odd Byte Address)
TBLPTR = xxxxx1
TBLPTR = xxxxx0
Instruction Register (IR)
FETCH
TBLRD
TABLAT Read Register
EXAMPLE 7-1:
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_WORD
READING A FLASH PROGRAM MEMORY WORD
CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word
TBLRD*+ MOVF MOVWF TBLRD*+ MOVF MOVWF
TABLAT, W WORD_EVEN TABLAT, W WORD_ODD
; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data
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7.4 Erasing Flash Program Memory
7.4.1
The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. TBLPTR<5:0> are ignored. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the Flash program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. For protection, the write initiate sequence for EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer.
FLASH PROGRAM MEMORY ERASE SEQUENCE
The sequence of events for erasing a block of internal program memory location is: 1. 2. Load Table Pointer register with address of row being erased. Set the EECON1 register for the erase operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN bit to enable writes; * set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the row erase cycle. The CPU will stall for duration of the erase (about 2 ms using internal timer). Re-enable interrupts.
3. 4. 5. 6. 7. 8.
EXAMPLE 7-2:
ERASING A FLASH PROGRAM MEMORY ROW
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EEPGD CFGS WREN FREE GIE ; load TBLPTR with the base ; address of the memory block
ERASE_ROW BSF BCF BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF ; ; ; ; ; point to Flash program memory access Flash program memory enable write to memory enable Row Erase operation disable interrupts
Required Sequence
; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts
WR GIE
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7.5 Writing to Flash Program Memory
The minimum programming block is 4 words or 8 bytes. Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 8 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 8 times for each programming operation. All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating the 8 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write. The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle. The long write will be terminated by the internal programming timer. The EEPROM on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note: The default value of the holding registers on device Resets and after write operations is FFh. A write of FFh to a holding register does not modify that byte. This means that individual bytes of program memory may be modified, provided that the change does not attempt to change any bit from a `0' to a `1'. When modifying individual bytes, it is not necessary to load all 8 holding registers before executing a write operation.
FIGURE 7-5:
TABLE WRITES TO FLASH PROGRAM MEMORY
TABLAT Write Register
8
TBLPTR = xxxxx0 TBLPTR = xxxxx1
8
TBLPTR = xxxxx2
8
TBLPTR = xxxxx7
8
Holding Register
Holding Register
Holding Register
Holding Register
Program Memory
7.5.1
FLASH PROGRAM MEMORY WRITE SEQUENCE
The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 8 bytes into RAM. Update data values in RAM as necessary. Load Table Pointer register with address being erased. Execute the row erase procedure. Load Table Pointer register with address of first byte being written. Write the 8 bytes into the holding registers with auto-increment. Set the EECON1 register for the write operation: * set EEPGD bit to point to program memory; * clear the CFGS bit to access program memory; * set WREN to enable byte writes.
Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit. This will begin the write cycle. The CPU will stall for duration of the write (about 2 ms using internal timer). 13. Re-enable interrupts. 14. Verify the memory (table read). This procedure will require about 6 ms to update one row of 8 bytes of memory. An example of the required code is given in Example 7-3. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the 8 bytes in the holding register.
8. 9. 10. 11. 12.
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EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY
MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_BLOCK TBLRD*+ MOVF MOVWF DECFSZ BRA MODIFY_WORD MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF ERASE_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BSF BCF BSF BSF BCF MOVLW Required MOVWF Sequence MOVLW MOVWF BSF BSF TBLRD*MOVLW MOVWF MOVLW MOVWF WRITE_BUFFER_BACK MOVLW MOVWF WRITE_BYTE_TO_HREGS MOVFF MOVWF TBLWT+* CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EEPGD EECON1, CFGS EECON1, WREN EECON1, FREE INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR INTCON, GIE BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L D'8 COUNTER POSTINC0, WREG TABLAT ; load TBLPTR with the base ; address of the memory block DATA_ADDR_HIGH FSR0H DATA_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; point to buffer TABLAT, W POSTINC0 COUNTER READ_BLOCK ; ; ; ; ; read into TABLAT, and inc get data store data done? repeat D'88 COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block ; point to buffer
; Load TBLPTR with the base ; address of the memory block
; update buffer word
; ; ; ; ;
point to Flash program memory access Flash program memory enable write to memory enable Row Erase operation disable interrupts
; write 55h ; ; ; ; ; write 0AAh start erase (CPU stall) re-enable interrupts dummy read decrement point to buffer
; number of bytes in holding register
DECFSZ COUNTER BRA WRITE_WORD_TO_HREGS
; ; ; ; ;
get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full
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EXAMPLE 7-3:
PROGRAM_MEMORY BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF EECON1, EECON1, EECON1, INTCON, 55h EECON2 0AAh EECON2 EECON1, INTCON, EECON1, EEPGD CFGS WREN GIE ; ; ; ; point to Flash program memory access Flash program memory enable write to memory disable interrupts
WRITING TO FLASH PROGRAM MEMORY (CONTINUED)
Required Sequence
; write 55h ; ; ; ; write 0AAh start program (CPU stall) re-enable interrupts disable write to memory
WR GIE WREN
7.5.2
WRITE VERIFY
7.5.4
Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit.
PROTECTION AGAINST SPURIOUS WRITES
To protect against spurious writes to Flash program memory, the write initiate sequence must also be followed. See Section 20.0 "Special Features of the CPU" for more detail.
7.5.3
UNEXPECTED TERMINATION OF WRITE OPERATION
7.6
If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and reprogrammed, if needed. If the write operation is interrupted by a MCLR Reset or a WDT Time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed.
Flash Program Operation During Code Protection
See Section 20.5 "Program Verification and Code Protection" for details on code protection of Flash program memory.
TABLE 7-2:
Name TBLPTRU TBPLTRH TBLPTRL TABLAT INTCON EECON2 EECON1 IPR2 PIR2 PIE2 Legend:
REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY
Bit 7 -- Bit 6 -- Bit 5 bit 21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: 47 47 47 47 INT0IE FREE EEIP EEIF EEIE RBIE WRERR -- -- -- TMR0IF WREN LVDIP LVDIF LVDIE INT0IF WR -- -- -- RBIF RD -- -- -- 47 49 49 49 49 49
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch GIE/GIEH EEPGD OSCFIP OSCFIF OSCFIE PEIE/GIEL CFGS -- -- -- TMR0IE -- -- -- -- EEPROM Control Register 2 (not a physical register)
-- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access.
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8.0 DATA EEPROM MEMORY
8.2 EECON1 and EECON2 Registers
The data EEPROM is readable and writable during normal operation over the entire VDD range. The data memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (SFR). There are four SFRs used to read and write the program and data EEPROM memory. These registers are: * * * * EECON1 EECON2 EEDATA EEADR Access to the data EEPROM is controlled by two registers: EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory. When clear, operations will access the data EEPROM memory. When set, program memory is accessed. Control bit, CFGS, determines if the access will be to the Configuration registers or to program memory/data EEPROM memory. When set, subsequent operations access Configuration registers. When CFGS is clear, the EEPGD bit selects either program Flash or data EEPROM memory. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WREN bit is set and cleared when the internal programming timer expires and the write operation is complete. Note 1: During normal operation, the WRERR bit is read as `1'. This can indicate that a write operation was prematurely terminated by a Reset, or a write operation was attempted improperly. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. 2: The Interrupt Flag bit, EEIF in the PIR2 register, is set when write is complete. It must be cleared in the software Control bits RD and WR, start read and erase/ write operations, respectively. These bits are set by firmware and cleared by hardware at the completion of the operation. The RD bit cannot be set when accessing program memory (EEPGD = 1). Program memory is read using table read instructions. See Section 7.1 "Table Reads and Table Writes" regarding table reads. Note: The EECON2 register is not a physical register. It is used exclusively in the memory write and erase sequences. Reading EECON2 will read all `0's.
The EEPROM data memory allows byte read and write. When interfacing to the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. These devices have 128 bytes of data EEPROM with an address range from 00h to FFh. The EEPROM data memory is rated for high erase/ write cycle endurance. A byte write automatically erases the location and writes the new data (erasebefore-write). The write time is controlled by an on-chip timer. The write time will vary with voltage and temperature, as well as from chip-to-chip. Please refer to parameter D122 (Table in Section 23.0 "Electrical Characteristics") for exact limits.
8.1
EEADR Register
The EEPROM Address register can address 256 bytes of data EEPROM.
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REGISTER 8-1:
R/W-x EEPGD bit 7 Legend: R = Readable bit -n = Value at POR bit 7 S = Settable bit W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
EECON1: EEPROM CONTROL REGISTER 1
R/W-x CFGS U-0 -- R/W-0 FREE R/W-x WRERR
(1)
R/W-0 WREN
R/S-0 WR
R/S-0 RD bit 0
EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory CFGS: Flash Program/Data EEPROM or Configuration Select bit 1 = Access Configuration registers 0 = Access Flash program or data EEPROM memory Unimplemented: Read as `0' FREE: Flash Row Erase Enable bit 1 = Erase the program memory row addressed by TBLPTR on the next WR command (cleared by completion of erase operation) 0 = Perform write-only WRERR: EEPROM Error Flag bit(1) 1 = A write operation is prematurely terminated (MCLR or WDT Reset during self-timed erase or program operation) 0 = The write operation completed WREN: Erase/Write Enable bit 1 = Allows erase/write cycles 0 = Inhibits erase/write cycles WR: Write Control bit 1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle. (The operation is self-timed and the bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to is completed RD: Read Control bit 1 = Initiates a memory read. (Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.) 0 = Read completed When a WRERR occurs, the EEPGD or FREE bit is not cleared. This allows tracing of the error condition.
bit 6
bit 5 bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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8.3 Reading the Data EEPROM Memory
After a write sequence has been initiated, EECON1, EEADR and EEDATA cannot be modified. The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must be set on a previous instruction. Both WR and WREN cannot be set with the same instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the EEPROM Interrupt Flag bit (EEIF) is set. The user may either enable this interrupt or poll this bit. EEIF must be cleared by software.
To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit RD (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).
8.4
Writing to the Data EEPROM Memory
8.5
Write Verify
To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 8-2 must be followed to initiate the write cycle. The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write 0AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM. The WREN bit is not cleared by hardware.
Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit.
8.6
Protection Against Spurious Write
There are conditions when the device may not want to write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared. Also, the Power-up Timer (72 ms duration) prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction.
EXAMPLE 8-1:
MOVLW MOVWF BCF BSF MOVF
DATA EEPROM READ
DATA_EE_ADDR EEADR EECON1, EEPGD EECON1, RD EEDATA, W ; ; ; ; ; Data Memory Address to read Point to DATA memory EEPROM Read W = EEDATA
EXAMPLE 8-2:
DATA EEPROM WRITE
; ; ; ; ; ; ; ; ; ; ; ; ; ; Data Memory Address to write Data Memory Value to write Point to DATA memory Enable writes Disable Interrupts Write 55h Write 0AAh Set WR bit to begin write Enable Interrupts Wait for write to complete
Required Sequence
MOVLW DATA_EE_ADDR MOVWF EEADR MOVLW DATA_EE_DATA MOVWF EEDATA BCF EECON1, EEPGD BSF EECON1, WREN BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE BTFSC EECON1, WR BRA $-2 SLEEP BCF EECON1, WREN
; Wait for interrupt to signal write complete ; Disable writes
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8.7 Operation During Code-Protect 8.8 Using the Data EEPROM
Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if either of these mechanisms are enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 20.0 "Special Features of the CPU" for additional information. The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124. If this is not the case, an array refresh must be performed. For this reason, variables that change infrequently (such as constants, IDs, calibration, etc.) should be stored in Flash program memory. A simple data EEPROM refresh routine is shown in Example 8-3. Note: If data EEPROM is only used to store constants and/or data that changes rarely, an array refresh is likely not required. See specification D124.
EXAMPLE 8-3:
CLRF BCF BCF BCF BSF LOOP BSF MOVLW MOVWF MOVLW MOVWF BSF BTFSC BRA INCFSZ BRA BCF BSF
DATA EEPROM REFRESH ROUTINE
EEADR EECON1, EECON1, INTCON, EECON1, CFGS EEPGD GIE WREN ; Start at address 0 ; Set for memory ; Set for Data EEPROM ; Disable interrupts ; Enable writes ; Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero, do it again ; Disable writes ; Enable interrupts
Required Sequence
EECON1, RD 55h EECON2 0AAh EECON2 EECON1, WR EECON1, WR $-2 EEADR, F LOOP EECON1, WREN INTCON, GIE
TABLE 8-1:
Name INTCON EEADR
REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY
Bit 7 Bit 6 PEIE/GIEL Bit 5 TMR0IE Bit 4 INT0IE Bit 3 RBIE Bit 2 TMR0IF Bit 1 INT0IF Bit 0 RBIF Reset Values on Page: 47 49 49 49 WREN LVDIP LVDIF LVDIE WR -- -- -- RD -- -- -- 49 49 49 49 -- -- -- -- FREE EEIP EEIF EEIE WRERR -- -- --
GIE/GIEH
EEPROM Address Register
EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) EECON1 IPR2 PIR2 PIE2 EEPGD OSCFIP OSCFIF OSCFIE CFGS -- -- --
Legend: -- = unimplemented, read as `0'. Shaded cells are not used during Flash/EEPROM access.
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9.0
9.1
8 x 8 HARDWARE MULTIPLIER
Introduction
EXAMPLE 9-1:
MOVF MULWF ARG1, W ARG2
8 x 8 UNSIGNED MULTIPLY ROUTINE
; ; ARG1 * ARG2 -> ; PRODH:PRODL
All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the Product register pair, PRODH:PRODL. The multiplier's operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. A comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in Table 9-1.
EXAMPLE 9-2:
MOVF MULWF BTFSC SUBWF MOVF BTFSC SUBWF ARG1, W ARG2 ARG2, SB PRODH, F ARG2, W ARG1, SB PRODH, F
8 x 8 SIGNED MULTIPLY ROUTINE
; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1
; Test Sign Bit ; PRODH = PRODH ; - ARG2
9.2
Operation
Example 9-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 9-2 shows the sequence to do an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument's Most Significant bit (MSb) is tested and the appropriate subtractions are done.
TABLE 9-1:
Routine
PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS
Multiply Method Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Program Memory (Words) 13 1 33 6 21 28 52 35 Cycles (Max) 69 1 91 6 242 28 254 40 Time @ 40 MHz 6.9 s 100 ns 9.1 s 600 ns 24.2 s 2.8 s 25.4 s 4.0 s @ 10 MHz 27.6 s 400 ns 36.4 s 2.4 s 96.8 s 11.2 s 102.6 s 16.0 s @ 4 MHz 69 s 1 s 91 s 6 s 242 s 28 s 254 s 40 s
8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed
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Example 9-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0).
EQUATION 9-2:
16 x 16 SIGNED MULTIPLICATION ALGORITHM
EQUATION 9-1:
16 x 16 UNSIGNED MULTIPLICATION ALGORITHM
RES3:RES0= ARG1H:ARG1L ARG2H:ARG2L = (ARG1H ARG2H 216) + (ARG1H ARG2L 28) + (ARG1L ARG2H 28) + (ARG1L ARG2L)
RES3:RES0= ARG1H:ARG1L ARG2H:ARG2L = (ARG1H ARG2H 216) + (ARG1H ARG2L 28) + (ARG1L ARG2H 28) + (ARG1L ARG2L) + (-1 ARG2H<7> ARG1H:ARG1L 216) + (-1 ARG1H<7> ARG2H:ARG2L 216)
EXAMPLE 9-4:
MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; BTFSS BRA MOVF SUBWF MOVF SUBWFB ; SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB ; CONT_CODE :
16 x 16 SIGNED MULTIPLY ROUTINE
EXAMPLE 9-3:
MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVFF MOVFF ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC
16 x 16 UNSIGNED MULTIPLY ROUTINE
ARG1L, W ARG2L
ARG1L, W ARG2L
; ARG1L * ARG2L -> ; PRODH:PRODL PRODH, RES1 ; PRODL, RES0 ; ARG1H, W ARG2H
; ARG1L * ARG2L-> ; PRODH:PRODL PRODH, RES1 ; PRODL, RES0 ; ARG1H, W ARG2H
; ARG1H * ARG2H -> ; PRODH:PRODL PRODH, RES3 ; PRODL, RES2 ; ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3
; ARG1H * ARG2H-> ; PRODH:PRODL PRODH, RES3 ; PRODL, RES2 ; ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
ARG1L * ARG2H-> PRODH:PRODL Add cross products
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ;
ARG1L * ARG2H -> PRODH:PRODL Add cross products
ARG1H * ARG2L -> PRODH:PRODL Add cross products
ARG1H * ARG2L-> PRODH:PRODL Add cross products
Example 9-4 shows the sequence to do a 16 x 16 signed multiply. Equation 9-2 shows the algorithm used. The 32-bit result is stored in four registers (RES3:RES0). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done.
; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ;
ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3
; ARG1H:ARG1L neg? ; no, done ; ; ;
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10.0 I/O PORTS
Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (Data Direction register) * PORT register (reads the levels on the pins of the device) * LAT register (Output Latch register) The Output Latch (LAT register) is useful for readmodify-write operations on the value that the I/O pins are driving. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 10-1. Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Output Latch (LATA) register is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. Pins RA6 and RA7 are multiplexed with the main oscillator pins; they are enabled as oscillator or I/O pins by the selection of the main oscillator in the Configuration register (see Section 20.1 "Configuration Bits" for details). When they are not used as port pins, RA6 and RA7 and their associated TRIS and LAT bits are read as `0'. The RA0 pin is multiplexed with one of the analog inputs, one of the external interrupt inputs, one of the interrupt-on-change inputs and one of the analog comparator inputs to become RA0/AN0/INT0/KBI0/ CMP0 pin. The RA1 pin is multiplexed with one of the analog inputs, one of the external interrupt inputs and one of the interrupt-on-change inputs to become RA1/AN1/ INT1/KBI1 pin. Pins RA2 and RA3 are multiplexed with the Enhanced USART transmission and reception input (see Section 20.1 "Configuration Bits" for details).
D CK Data Latch D WR TRIS CK TRIS Latch RD TRIS Input Buffer Q Q I/O pin(1)
FIGURE 10-1:
GENERIC I/O PORT OPERATION
RD LAT Data Bus WR LAT or Port
The RA4 pin is multiplexed with the Timer0 module clock input, one of the analog inputs and the analog VREF+ input to become the RA4/T0CKI/AN2/VREF+ pin. The Fault detect input for PWM FLTA is multiplexed with pins RA5 and RA7. Its placement is decided by clearing or setting the FLTAMX bit of Configuration Register 3H. Note: On a Power-on Reset, RA0, RA1, RA4 and RA5 are configured as analog inputs and read as `0'. RA2 and RA3 are configured as digital inputs.
Q
D EN EN
The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.
RD Port Note 1: I/O pins have diode protection to VDD and VSS.
EXAMPLE 10-1:
CLRF ; ; ; LATA ; ; ; 07h ; ADCON1 ; 07h ; CMCON ; 0CFh ; ; ; TRISA ; ; PORTA
INITIALIZING PORTA
Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Configure comparators for digital input Value used to initialize data direction Set RA<7:6,3:0> as inputs RA<5:4> as outputs
CLRF
10.1
PORTA, TRISA and LATA Registers
MOVLW MOVWF MOVWF MOVWF MOVLW
PORTA is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin).
MOVWF
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TABLE 10-1:
Pin RA0/AN0/INT0/ KBI0/CMP0
PORTA I/O SUMMARY
Function RA0 AN0 INT0 KBI0 CMP0 TRIS Setting 0 1 1 1 1 1 0 1 AN1 INT1 KBI1 1 1 1 0 1 TX CK 0 0 1 I/O O I I I I I O I I I I O I 0 O I O I I O I O I I I I I I I I O I O O O I I O I I I I I I/O Type DIG TTL ANA ST TTL ANA DIG TTL ANA ST TTL DIG TTL DIG DIG ST DIG TTL ANA DIG TTL DIG ST ST ANA ANA ST ANA ST ST DIG ST ANA ANA ANA ST ANA DIG TTL ANA ANA ANA ST LATA<4> data output. PORTA<4> data input; default configuration on POR. Timer0 external clock input. Analog input 2. A/D reference voltage (high) input. Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. Fault detect input for PWM. LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only. PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes only. Oscillator crystal output or external clock source output. Oscillator crystal output. Timer1 oscillator output. Timer1 clock input. Analog input 3. LATA<7> data output. Disabled in external oscillator modes. PORTA<7> data input. Disabled in external oscillator modes. Oscillator crystal input or external clock source input. External clock source input. Timer1 oscillator input. Fault detect input for PWM. LATA<3> data output; not affected by analog input. PORTA<3> data input; disabled when analog input enabled. EUSART asynchronous receive. EUSART synchronous data. Description LATA<0> data output; not affected by analog input. PORTA<0> data input; disabled when analog input enabled. Analog input 0. External interrupt 0. Interrupt-on-change pin. Comparator 0 input. LATA<1> data output; not affected by analog input. PORTA<1> data input; disabled when analog input enabled. Analog input 1. External interrupt 1. Interrupt-on-change pin. LATA<2> data output; not affected by analog input. Disabled when CVREF output enabled. PORTA<2> data input. Disabled when analog functions enabled; disabled when CVREF output enabled. EUSART asynchronous transmit. EUSART synchronous clock.
RA1/AN1/INT1/ KBI1
RA1
RA2/TX/CK
RA2
RA3/RX/DT
RA3 RX DT
0 1 1 0 1
RA4/T0CKI/AN2/ VREF+
RA4 T0CKI AN2 VREF+
0 1 1 1 1 1 1 1 1 0 1
MCLR/VPP/RA5/ FLTA
MCLR VPP RA5 FLTA
(1)
RA6/OSC2/CLKO/ T1OSO/T1CKI/AN3
RA6 OSC2 CLKO T1OSO(2) T1CKI(2) AN3
0 0 0 1 1 0 1 1 1 1 1
RA7/OSC1/CLKI/ T1OSI/FLTA
RA7 OSC1 CLKI T1OSI
(2)
FLTA(1) Legend: Note 1: 2:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Placement of FLTA depends on the value of Configuration bit, FLTAMX, of CONFIG3H. Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H.
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TABLE 10-2:
Name PORTA LATA TRISA INTCON INTCON2 ADCON1 CMCON CVRCON
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 RA7(1) LATA7
(1)
Bit 6 RA6(1) LATA6(1)
Bit 5 RA5
Bit 4 RA4
Bit 3 RA3
Bit 2 RA2
Bit 1 RA1
Bit 0 RA0
Reset Values on Page: 50 49 49 47 47 48 48 48
PORTA Output Latch Register (Read and Write to Data Latch) TMR0IE -- C0OUT CVRR INT0IE VCFG0 -- CVRSS RBIE PCFG3 -- CVR3 TMR0IF TMR0IP PCFG2 CMEN2 CVR2 INT0IF INT3IP PCFG1 CMEN1 CVR1 RBIF RBIP PCFG0 CMEN0 CVR0
TRISA7(1) TRISA6(1) PORTA Data Direction Control Register GIE/GIEH PEIE/GIEL RBPU -- C2OUT CVREN INTEDG0 -- C1OUT -- INTEDG1 INTEDG2 INTEDG3
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as `0'.
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10.2 PORTB, TRISB and LATB Registers
Pins RB0, RB1 and RB4:RB7 are multiplexed with the Power Control PWM outputs. Pins RB2 and RB3 are multiplexed with external interrupt inputs, interrupt-on-change input, the analog comparator inputs and the Timer1 oscillator input and output to become RB2/INT2/KBI2/CMP2/T1OSO/T1CKI and RB3/INT3/KNBI3/CMP1/T1OSI, respectively. When the interrupt-on-change feature is enabled, only pins configured as inputs can cause this interrupt to occur (i.e., any RB2, RB3, RA0 and RA1 pin configured as an output is excluded from the interrupt-on-change comparison). The input pins (RB2, RB3, RA0 and RA1) are compared with the old value latched on the last read of PORTA and PORTB. The "mismatch" outputs of these pins are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON<0>). This interrupt can wake the device from Sleep mode, or any of the Idle modes. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) c) Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). 1 TCY Clear flag bit, RBIF.
PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Output Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB.
EXAMPLE 10-2:
CLRF PORTB ; ; ; LATB ; ; ; 0Fh ; ADCON1 ; ; ; 0CFh ; ; ; TRISB ; ; ;
INITIALIZING PORTB
Initialize PORTB by clearing output data latches Alternate method to clear output data latches Set RB<4:0> as digital I/O pins (required if config bit PBADEN is set) Value used to initialize data direction Set RB<3:0> as inputs RB<5:4> as outputs RB<7:6> as inputs
CLRF
MOVLW MOVWF
MOVLW
MOVWF
A mismatch condition will continue to set flag bit, RBIF. Reading PORTB and waiting 1 TCY will end the mismatch condition and allow flag bit, RBIF, to be cleared. Additionally, if the port pin returns to its original state, the mismatch condition will be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTA and PORTB are used for the interrupton-change feature. Polling of PORTA and PORTB is not recommended while using the interrupt-on-change feature.
Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Note: On a Power-on Reset, PORTB is configured as digital inputs except for RB2 and RB3. RB2 and RB3 are configured as analog inputs when the T1OSCMX bit of Configuration Register 3H is cleared. Otherwise, RB2 and RB3 are also configured as digital inputs.
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TABLE 10-3:
Pin RB0/PWM0
PORTB I/O SUMMARY
Function RB0 TRIS Setting 0 1 PWM0 0 0 1 PWM1 0 0 1 INT2 KBI2 CMP2 T1OSO(2) T1CKI(2) 1 1 1 0 1 0 1 INT3 KBI3 CMP1 T1OSI(2) 1 1 1 1 0 1 PWM2 0 0 1 PWM3 0 0 1 PWM4 PGC 0 1 0 1 PWM5 PGD 0 0 I/O O I O O I O O I I I I O I O I I I I I O I O O I O O I O I O I O O I/O Type DIG TTL DIG DIG TTL DIG DIG TTL ST TTL ANA ANA ST DIG TTL ST TTL ANA ANA DIG TTL DIG DIG TTL DIG DIG TTL DIG ST DIG TTL TTL DIG Description LATB<0> data output; not affected by analog input. PORTB<0> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) PWM module output PWM0. LATB<1> data output; not affected by analog input. PORTB<1> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) PWM module output PWM1. LATB<2> data output; not affected by analog input. PORTB<2> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) External interrupt 2 input. Interrupt-on-change pin. Comparator 2 input. Timer1 oscillator output. Timer1 clock input. LATB<3> data output; not affected by analog input. PORTB<3> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) External interrupt 3 input. Interrupt-on-change pin. Comparator 1 input. Timer1 oscillator input. LATB<4> data output; not affected by analog input. PORTB<4> data input; weak pull-up when RBPU bit is cleared. Disabled when analog input enabled.(1) PWM module output PWM2. LATB<5> data output. PORTB<5> data input; weak pull-up when RBPU bit is cleared. PWM module output PWM3. LATB<6> data output. PORTB<6> data input; weak pull-up when RBPU bit is cleared. PWM module output PWM4. In-Circuit Debugger and ICSPTM programming clock pin. LATB<7> data output. PORTB<7> data input; weak pull-up when RBPU bit is cleared. PWM module output PWM4. In-Circuit Debugger and ICSP programming data pin.
RB1PWM1
RB1
RB2/INT2/KBI2/ CMP2/T1OSO/ T1CKI
RB2
RB3/INT3/KBI3/ CMP1/T1OSI
RB3
RB4/PWM2
RB4
RB5/PWM3
RB5
RB6/PWM4/PGC
RB6
RB7/PWM5/PGD
RB7
Legend: Note 1: 2:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don't care (TRIS bit does not affect port direction or is overridden for this option). Configuration on POR is determined by the PBADEN Configuration bit. Pins are configured as analog inputs by default when PBADEN is set and digital inputs when PBADEN is cleared. Placement of T1OSI and T1OSO/T1CKI depends on the value of Configuration bit, T1OSCMX, of CONFIG3H.
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TABLE 10-4:
Name PORTB LATB TRISB INTCON INTCON2 INTCON3 CMCON
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Bit 7 RB7 Bit 6 RB6 Bit 5 RB5 Bit 4 RB4 Bit 3 RB3 Bit 2 RB2 Bit 1 RB1 Bit 0 RB0 Reset Values on Page: 50 49 49 RBIE INT1IE -- TMR0IF INT3IF CMEN2 INT0IF INT3IP INT2IF CMEN1 RBIF RBIP INT1IF CMEN0 47 47 47 48
PORTB Output Latch Register (Read and Write to Data Latch) PORTB Data Direction Control Register GIE/GIEH PEIE/GIEL RBPU INT2IP C2OUT INT1IP C1OUT TMR0IE INT3IE C0OUT INT0IE INT2IE -- INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by PORTB.
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11.0 INTERRUPTS
The PIC18F1230/1330 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress. There are thirteen registers which are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON<6> is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON<7> is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 0008h in Compatibility mode. When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a lowpriority interrupt. Low-priority interrupts are not processed while high-priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit. Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.
It is recommended that the Microchip header files supplied with MPLAB(R) IDE be used for the symbolic bit names in these registers. This allows the assembler/ compiler to automatically take care of the placement of these bits within the specified register. In general, interrupt sources have three bits to control their operation. They are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON<7>). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON<7>) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON<6>) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits.
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FIGURE 11-1: PIC18 INTERRUPT LOGIC
TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Wake-up if in Idle or Sleep modes
Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit ADIF ADIE ADIP From Power Control PWM Interrupt Logic PTIF PTIE PTIP Additional Peripheral Interrupts High-Priority Interrupt Generation Low-Priority Interrupt Generation
Interrupt to CPU Vector to Location 0008h
GIE/GIEH IPEN IPEN PEIE/GIEL IPEN
Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Interrupt to CPU Vector to Location 0018h
ADIF ADIE ADIP From Power Control PWM Interrupt Logic PTIF PTIE PTIP
GIE/GIEH PEIE/GIEL
Additional Peripheral Interrupts
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11.1 INTCON Registers
Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
REGISTER 11-1:
R/W-0 GIE/GIEH bit 7 Legend: R = Readable bit -n = Value at POR bit 7
INTCON: INTERRUPT CONTROL REGISTER
R/W-0 R/W-0 TMR0IE R/W-0 INT0IE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF(1) bit 0
PEIE/GIEL
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 11-2:
R/W-1 RBPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1 R/W-1 INTEDG1 R/W-1 INTEDG2 R/W-1 INTEDG3 R/W-1 TMR0IP R/W-1 INT3IP R/W-1 RBIP bit 0
INTEDG0
RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
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REGISTER 11-3:
R/W-1 INT2IP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
INTCON3: INTERRUPT CONTROL REGISTER 3
R/W-1 INT1IP R/W-0 INT3IE R/W-0 INT2IE R/W-0 INT1IE R/W-0 INT3IF R/W-0 INT2IF R/W-0 INT1IF bit 0
INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
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11.2 PIR Registers
The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2 and PIR3). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON<7>). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt.
REGISTER 11-4:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 CMP2IF R/W-0 CMP1IF R/W-0 CMP0IF R/W-0 TMR1IF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RCIF: EUSART Receive Interrupt Flag bit 1 = The EUSART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The EUSART receive buffer is empty TXIF: EUSART Transmit Interrupt Flag bit 1 = The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The EUSART transmit buffer is full CMP2IF: Analog Comparator 2 Flag bit 1 = The output of CMP2 has changed since last read 0 = The output of CMP2 has not changed since last read CMP1IF: Analog Comparator 1 Flag bit 1 = The output of CMP1 has changed since last read 0 = The output of CMP1 has not changed since last read CMP0IF: Analog Comparator 0 Flag bit 1 = The output of CMP0 has changed since last read 0 = The output of CMP0 has not changed since last read TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 11-5:
R/W-0 OSCFIF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2
U-0 -- U-0 -- R/W-0 EEIF U-0 -- R/W-0 LVDIF U-0 -- U-0 -- bit 0
OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = Device clock operating Unimplemented: Read as `0' EEIF: Data EEPROM/Flash Write Operation Interrupt Flag bit 1 = The write operation is complete (must be cleared in software) 0 = The write operation is not complete or has not been started Unimplemented: Read as `0' LVDIF: Low-Voltage Detect Interrupt Flag bit 1 = A low-voltage condition occurred 0 = A low-voltage condition has not occurred Unimplemented: Read as `0'
bit 6-5 bit 4
bit 3 bit 2
bit 1-0
REGISTER 11-6:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4
PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3
U-0 -- U-0 -- R/W-0 PTIF U-0 -- U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' PTIF: PWM Time Base Interrupt bit 1 = PWM time base matched the value in PTPER register. Interrupt is issued according to the postscaler settings. PTIF must be cleared in software. 0 = PWM time base has not matched the value in PTPER register Unimplemented: Read as `0'
bit 3-0
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11.3 PIE Registers
The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2 and PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
REGISTER 11-7:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0 ADIE R-0 RCIE R-0 TXIE R/W-0 CMP2IE R/W-0 CMP1IE R/W-0 CMP0IE R/W-0 TMR1IE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RCIE: EUSART Receive Interrupt Enable bit 1 = Enables the EUSART receive interrupt 0 = Disables the EUSART receive interrupt TXIE: EUSART Transmit Interrupt Enable bit 1 = Enables the EUSART transmit interrupt 0 = Disables the EUSART transmit interrupt CMP2IE: Analog Comparator 2 Interrupt Enable bit 1 = Enables the CMP2 interrupt 0 = Disables the CMP2 interrupt CMP1IE: Analog Comparator 1 Interrupt Enable bit 1 = Enables the CMP1 interrupt 0 = Disables the CMP1 interrupt CMP0IE: Analog Comparator 0 Interrupt Enable bit 1 = Enables the CMP0 interrupt 0 = Disables the CMP0 interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 11-8:
R/W-0 OSCFIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2
U-0 -- U-0 -- R/W-0 EEIE U-0 -- R/W-0 LVDIE U-0 -- U-0 -- bit 0
OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0'
bit 6-5 bit 4
bit 3 bit 2
bit 1-0
REGISTER 11-9:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4
PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3
U-0 -- U-0 -- R/W-0 PTIE U-0 -- U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' PTIE: PWM Time Base Interrupt Enable bit 1 = PWM enabled 0 = PWM disabled Unimplemented: Read as `0'
bit 3-0
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11.4 IPR Registers
The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
REGISTER 11-10: IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1 ADIP R/W-1 RCIP R/W-1 TXIP R/W-1 CMP2IP R/W-1 CMP1IP R/W-1 CMP0IP R/W-1 TMR1IP bit 0
Unimplemented: Read as `0' ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority RCIP: EUSART Receive Interrupt Priority bit 1 = High priority 0 = Low priority TXIP: EUSART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority
bit 5
bit 4
bit 3
CMP2IP: Analog Comparator 2 Interrupt Priority bit 1 = CMP2 is high priority 0 = CMP2 is low priority CMP1IP: Analog Comparator 1 Interrupt Priority bit 1 = CMP1 is high priority 0 = CMP1 is low priority CMP0IP: Analog Comparator 0 Interrupt Priority bit 1 = CMP0 is high priority 0 = CMP0 is low priority TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority
bit 2
bit 1
bit 0
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REGISTER 11-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2
R/W-1 OSCFIP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-1 EEIP U-0 -- R/W-1 LVDIP U-0 -- U-0 -- bit 0
OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0' LVDIP: Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0'
bit 6-5 bit 4
bit 3 bit 2
bit 1-0
REGISTER 11-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-1 PTIP U-0 -- U-0 -- U-0 -- U-0 -- bit 0
Unimplemented: Read as `0' PTIP: PWM Time Base Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as `0'
bit 3-0
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11.5 RCON Register
The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section 5.1 "RCON Register".
REGISTER 11-13: RCON: RESET CONTROL REGISTER
R/W-0 IPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-1(1) SBOREN U-0 -- R/W-1 RI R-1 TO R-1 PD R/W-0(2) POR R/W-0 BOR bit 0
IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) SBOREN: BOR Software Enable bit(1) For details of bit operation, see Register 5-1. Unimplemented: Read as `0' RI: RESET Instruction Flag bit For details of bit operation, see Register 5-1. TO: Watchdog Time-out Flag bit For details of bit operation, see Register 5-1. PD: Power-Down Detection Flag bit For details of bit operation, see Register 5-1. POR: Power-on Reset Status bit(2) For details of bit operation, see Register 5-1. BOR: Brown-out Reset Status bit For details of bit operation, see Register 5-1. If SBOREN is enabled, its Reset state is `1'; otherwise, it is `0'. See Register 5-1 for additional information. The actual Reset value of POR is determined by the type of device Reset. See Register 5-1 for additional information.
bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
Note 1: 2:
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11.6 INTx Pin Interrupts 11.7 TMR0 Interrupt
External interrupts on the RA0/INT0, RA1/INT1, RB2/ INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the pin, the corresponding flag bit, INTxIF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE. Flag bit, INTxIF, must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1, INT2 and INT3) can wake-up the processor from Idle or Sleep modes if bit INTxIE was set prior to going into those modes. If the Global Interrupt Enable bit, GIE, is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1, INT2 and INT3 is determined by the value contained in the interrupt priority bits, INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and INT3IP (INTCON2<1>). There is no priority bit associated with INT0. It is always a high-priority interrupt source. In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh 00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register pair (FFFFh 0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON<5>). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2<2>). See Section 12.0 "Timer0 Module" for further details on the Timer0 module.
11.8
Interrupt-on-Change
An input change on PORTA<1:0> and/or PORTB<2:3> sets flag bit, RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON<3>). Interrupt priority for interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2<0>).
11.9
Context Saving During Interrupts
During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (see Section 6.3 "Data Memory Organization"), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user's application, other registers may also need to be saved. Example 11-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine.
EXAMPLE 11-1:
MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere
W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP, STATUS
; Restore BSR ; Restore WREG ; Restore STATUS
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12.0 TIMER0 MODULE
The Timer0 module has the following features: * Software selectable as an 8-bit or 16-bit timer/counter * Readable and writable * Dedicated 8-bit software programmable prescaler * Clock source selectable to be external or internal * Interrupt on overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode * Edge select for external clock Figure 12-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 12-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 12-1) is a readable and writable register that controls all the aspects of Timer0, including the prescale selection.
REGISTER 12-1:
R/W-1 TMR0ON bit 7 Legend: R = Readable bit -n = Value at POR bit 7
T0CON: TIMER0 CONTROL REGISTER
R/W-1 R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 T0PS2 R/W-1 T0PS1 R/W-1 T0PS0 bit 0
T016BIT
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 T016BIT: Timer0 16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin input edge 0 = Internal clock (FOSC/4) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value
bit 6
bit 5
bit 4
bit 3
bit 2-0
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FIGURE 12-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE
Data Bus FOSC/4 T0CKI pin 1 Programmable Prescaler 3 T0PS2, T0PS1, T0PS0 T0CS 0 (2 TCY Delay) PSA Set Interrupt Flag bit TMR0IF on Overflow 0 1 Sync with Internal Clocks TMR0 8
T0SE
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
FIGURE 12-2:
FOSC/4
TIMER0 BLOCK DIAGRAM IN 16-BIT MODE
T0CKI pin
0 1 1 Programmable Prescaler 3 T0PS2, T0PS1, T0PS0 T0CS PSA 8 8 TMR0H 8 Data Bus<7:0> 0 Sync with Internal Clocks (2 TCY Delay) TMR0L TMR0 High Byte 8 Set Interrupt Flag bit TMR0IF on Overflow
T0SE
Read TMR0L Write TMR0L
Note:
Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI maximum prescale.
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12.1 Timer0 Operation
12.2.1
Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI/AN2/VREF+. The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the T0SE bit selects the rising edge. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization.
SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution).
12.3
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF bit. The interrupt can be masked by clearing the TMR0IE bit. The TMR0IF bit must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from Sleep mode, since the timer requires clock cycles even when T0CS is set.
12.4
16-Bit Mode Timer Reads and Writes
12.2
Prescaler
An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable. The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, x..., etc.) will clear the prescaler count. Note: Writing to TMR0, when the prescaler is assigned to Timer0, will clear the prescaler count but will not change the prescaler assignment.
TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of Timer0 (refer to Figure 12-2). The high byte of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte. A write to the high byte of Timer0 must also take place through the TMR0H Buffer register. Timer0 high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once.
TABLE 12-1:
Name TMR0L TMR0H INTCON T0CON TRISA
REGISTERS ASSOCIATED WITH TIMER0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: 48 48 TMR0IE T0CS INT0IE T0SE RBIE PSA TMR0IF T0PS2 INT0IF T0PS1 RBIF T0PS0 47 48 49
Timer0 Register Low Byte Timer0 Register High Byte GIE/GIEH TMR0ON RA7(1) PEIE/GIEL T016BIT RA6(1)
PORTA Data Direction Control Register
Legend: -- = unimplemented locations read as `0'. Shaded cells are not used by Timer0. Note 1: RA6 and RA7 are enabled as I/O pins depending on the oscillator mode selected in CONFIG1H.
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13.0 TIMER1 MODULE
The Timer1 timer/counter module has the following features: * 16-bit timer/counter (two 8-bit registers; TMR1H and TMR1L) * Readable and writable (both registers) * Internal or external clock select * Interrupt on overflow from FFFFh to 0000h * Status of system clock operation Figure 13-1 is a simplified block diagram of the Timer1 module. Register 13-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON<0>). The Timer1 oscillator can be used as a secondary clock source in power-managed modes. When the T1RUN bit is set, the Timer1 oscillator provides the system clock. If the Fail-Safe Clock Monitor is enabled and the Timer1 oscillator fails while providing the system clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead.
REGISTER 13-1:
R/W-0 RD16 bit 7 Legend: R = Readable bit -n = Value at POR bit 7
T1CON: TIMER1 CONTROL REGISTER
R-0 R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0
T1RUN
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations T1RUN: Timer1 System Clock Status bit 1 = Device clock is derived from Timer1 oscillator 0 = Device clock is derived from another source T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 oscillator is enabled 0 = Timer1 oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from T1OSO/T1CKI (on the rising edge)(1) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1
bit 6
bit 5-4
bit 3
bit 2
bit 1
bit 0
Note 1: Placement of T1OSI and T1OSO/T1CKI depends on the value of the Configuration bit, T1OSCMX, of CONFIG3H.
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13.1 Timer1 Operation
Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The operating mode is determined by the Clock Select bit, TMR1CS (T1CON<1>). When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the T1OSI and T1OSO/T1CKI pins become inputs. That is, the corresponding TRISA bit value is ignored, and the pins are read as `0'.
FIGURE 13-1:
TMR1IF Overflow Interrupt Flag Bit
TIMER1 BLOCK DIAGRAM
Synchronized Clock Input
TMR1 TMR1H TMR1L
0
1 TMR1ON On/Off T1OSO/T1CKI T1OSI T1OSC T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. Peripheral Clocks T1SYNC Synchronize det
FIGURE 13-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
Data Bus<7:0> 8
TMR1H
Write TMR1L Read TMR1L TMR1IF Overflow Interrupt Flag bit 8
8
8
TMR1 Timer1 High Byte TMR1L
0 1 TMR1ON On/Off T1SYNC
Synchronized Clock Input
T1OSC T1OSO/T1CKI T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock 1 0 TMR1CS 2 Peripheral Clocks Prescaler 1, 2, 4, 8 Synchronize det
T1OSI
T1CKPS1:T1CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
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13.2 Timer1 Oscillator
13.2.1
A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO/TICKI (amplifier output). The placement of these pins depends on the value of Configuration bit, T1OSCMX (see Section 20.1 "Configuration Bits"). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated for 32 kHz crystals. It will continue to run during all power-managed modes. The circuit for a typical LP oscillator is shown in Figure 13-3. Table 13-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator.
USING TIMER1 AS A CLOCK SOURCE
The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the System Clock Select bits, SCS1:SCS0 (OSCCON<1:0>), to `01', the device switches to SEC_RUN mode; both the CPU and peripherals are clocked from the Timer1 oscillator. If the IDLEN bit (OSCCON<7>) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE mode. Additional details are available in Section 4.0 "Power-Managed Modes". Whenever the Timer1 oscillator is providing the clock source, the Timer1 system clock status flag, T1RUN (T1CON<6>), is set. This can be used to determine the controller's current clocking mode. It can also indicate the clock source being currently used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source.
FIGURE 13-3:
EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR
PIC18FXXXX
T1OSI XTAL 32.768 kHz T1OSO/T1CKI
C1 33 pF
13.3
Timer1 Oscillator Layout Considerations
C2 33 pF Note: See the notes with Table 13-1 for additional information about capacitor selec-
The oscillator circuit, shown in Figure 13-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the oscillator (such as the PWM pin, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as shown in Figure 13-4, may be helpful when used on a single-sided PCB, or in addition to a ground plane.
TABLE 13-1:
Osc Type LP
CAPACITOR SELECTION FOR THE TIMER OSCILLATOR
Freq 32 kHz 27 C1 pF(1) C2 27 pF(1)
FIGURE 13-4:
Note 1: Microchip suggests this value as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only.
VDD RB3 RB2
OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING
OSC1 OSC2
Note: Not drawn to scale.
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13.4 Timer1 Interrupt 13.6 Using Timer1 as a Real-Time Clock
The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing Timer1 interrupt enable bit, TMR1IE (PIE1<0>). Adding an external LP oscillator to Timer1 (such as the one described in Section 13.2 "Timer1 Oscillator"), gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. When operating in Sleep mode and using a battery or super capacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 13-1, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by one. Additional counters for minutes and hours are incremented as the previous counter overflow. Since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it. The simplest method is to set the MSb of TMR1H with a BSF instruction. Note that the TMR1L register is never preloaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times.
13.5
Timer1 16-Bit Read/Write Mode
Timer1 can be configured for 16-bit reads and writes (see Figure 13-2). When the RD16 control bit (T1CON<7>) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, is valid due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L.
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EXAMPLE 13-1:
RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN RTCisr BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN MOVLW MOVWF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .59 secs secs mins, F .59 mins mins hours, F .23 hours .01 hours ; ; ; ; ; ; ; ; ; ; ; ; Preload for 1 sec overflow Clear interrupt flag Increment seconds 60 seconds elapsed? No, done Clear seconds Increment minutes 60 minutes elapsed? No, done clear minutes Increment hours 24 hours elapsed? 0x80 TMR1H TMR1L b'00001111' T1CON secs mins .12 hours PIE1, TMR1IE ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ;
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
; Enable Timer1 interrupt
; No, done ; Reset hours to 1 ; Done
TABLE 13-2:
Name INTCON PIR1 PIE1 IPR1 TMR1L TMR1H T1CON
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 Bit 6 PEIE/GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE CMP2IF CMP2IE CMP2IP Bit 2 TMR0IF CMP1IF CMP1IE CMP1IP Bit 1 INT0IF CMP0IF CMP0IE CMP0IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Reset Values on Page: 47 49 49 49 48 48 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 48
GIE/GIEH -- -- --
Timer1 Register Low Byte Timer1 Register High Byte RD16 T1RUN
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
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14.0 POWER CONTROL PWM MODULE
The PWM module has the following features: * Up to six PWM I/O pins with three duty cycle generators. Pins can be paired to acquire a complete half-bridge control. * Up to 14-bit resolution, depending upon the PWM period. * "On-the-fly" PWM frequency changes. * Edge and Center-Aligned Output modes. * Single-Pulse Generation mode. * Programmable dead-time control between paired PWMs. * Interrupt support for asymmetrical updates in Center-Aligned mode. * Output override for Electrically Commutated Motor (ECM) operation; for example, BLDC. * Special Event Trigger comparator for triggering A/D conversion. * PWM outputs disable feature sets PWM outputs to their inactive state when in Debug mode. The Power Control PWM module supports three PWM generators and six output channels on PIC18F1230/ 1330 devices. A simplified block diagram of the module is shown in Figure 14-1. Figure 14-2 and Figure 14-3 show how the module hardware is configured for each PWM output pair for the Complementary and Independent Output modes. Each functional unit of the PWM module will be discussed in subsequent sections.
The Power Control PWM module simplifies the task of generating multiple, synchronized Pulse-Width Modulated (PWM) outputs for use in the control of motor controllers and power conversion applications. In particular, the following power and motion control applications are supported by the PWM module: * Three-Phase and Single-Phase AC Induction Motors * Switched Reluctance Motors * Brushless DC (BLDC) Motors * Uninterruptible Power Supplies (UPS) * Multiple DC Brush Motors
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FIGURE 14-1:
Internal Data Bus
8
POWER CONTROL PWM MODULE BLOCK DIAGRAM
PWMCON0
8
PWM Enable and Mode PWMCON1
8
DTCON
8
Dead-Time Control
FLTCONFIG
8
Fault Pin Control
OVDCON
PWM Manual Control PWM Generator #2(1) PDC2 Buffer
8
PDC2 Channel 2 Dead-Time Generator and Override Logic(1) Channel 1 Dead-Time Generator and Override Logic Channel 0 Dead-Time Generator and Override Logic
Comparator
PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
8
PTMR Comparator
PWM Generator 1
Output Driver Block
PWM Generator 0 PTPER
8
PTPER Buffer
8
FLTA
PTCONx
Comparator
8
SEVTDIR SEVTCMP PTDIR
Special Event Postscaler
Special Event Trigger
Note 1:
Only PWM Generator 2 is shown in detail. The other generators are identical; their details are omitted for clarity.
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FIGURE 14-2: PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, COMPLEMENTARY MODE
VDD
Dead-Band Generator Duty Cycle Comparator HPOL
PWM1
PWM Duty Cycle Register
PWM0
LPOL Fault Override Values Channel Override Values Fault Pin Assignment Logic
Fault A pin
Note:
In the Complementary mode, the even channel cannot be forced active by a Fault or override event when the odd channel is active. The even channel is always the complement of the odd channel and is inactive, with dead time inserted, before the odd channel is driven to its active state.
FIGURE 14-3:
PWM MODULE BLOCK DIAGRAM, ONE OUTPUT PAIR, INDEPENDENT MODE
VDD
PWM Duty Cycle Register PWM1 HPOL
Duty Cycle Comparator VDD
PWM0
Fault Override Values Channel Override Values Fault Pin Assignment Logic
LPOL
Fault A pin
This module contains three duty cycle generators, numbered 0 through 2. The module has six PWM output pins, numbered 0 through 5. The six PWM outputs are grouped into output pairs of even and odd numbered outputs. In Complementary modes, the even PWM pins must always be the complement of the corresponding odd PWM pins. For example, PWM0 will be the complement of PWM1 and PWM2 will be the complement of PWM3. The dead-time generator
inserts an OFF period called "dead time" between the going OFF of one pin to the going ON of the complementary pin of the paired pins. This is to prevent damage to the power switching devices that will be connected to the PWM output pins. The time base for the PWM module is provided by its own 12-bit timer, which also incorporates selectable prescaler and postscaler options.
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14.1 Control Registers 14.2 Module Functionality
The operation of the PWM module is controlled by a total of 20 registers. Eight of these are used to configure the features of the module: * * * * * * * * PWM Timer Control Register 0 (PTCON0) PWM Timer Control Register 1 (PTCON1) PWM Control Register 0 (PWMCON0) PWM Control Register 1 (PWMCON1) Dead-Time Control Register (DTCON) Output Override Control Register (OVDCOND) Output State Register (OVDCONS) Fault Configuration Register (FLTCONFIG) The PWM module supports several modes of operation that are beneficial for specific power and motor control applications. Each mode of operation is described in subsequent sections. The PWM module is composed of several functional blocks. The operation of each is explained separately in relation to the several modes of operation: * * * * * * * * PWM Time Base PWM Time Base Interrupts PWM Period PWM Duty Cycle Dead-Time Generators PWM Output Overrides PWM Fault Inputs PWM Special Event Trigger
There are also 12 registers that are configured as six register pairs of 16 bits. These are used for the configuration values of specific features. They are: * PWM Time Base Registers (PTMRH and PTMRL) * PWM Time Base Period Registers (PTPERH and PTPERL) * PWM Special Event Compare Registers (SEVTCMPH and SEVTCMPL) * PWM Duty Cycle #0 Registers (PDC0H and PDC0L) * PWM Duty Cycle #1 Registers (PDC1H and PDC1L) * PWM Duty Cycle #2 Registers (PDC2H and PDC2L) All of these register pairs are double-buffered.
14.3
PWM Time Base
The PWM time base is provided by a 12-bit timer with prescaler and postscaler functions. A simplified block diagram of the PWM time base is shown in Figure 14-4. The PWM time base is configured through the PTCON0 and PTCON1 registers. The time base is enabled or disabled by respectively setting or clearing the PTEN bit in the PTCON1 register. Note: The PTMR register pair (PTMRL:PTMRH) is not cleared when the PTEN bit is cleared in software.
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FIGURE 14-4: PWM TIME BASE BLOCK DIAGRAM
PTMR Register PTMR Clock
Timer Reset Up/Down
Comparator
Zero Match Timer Direction Control PTDIR Duty Cycle Load
Comparator
Period Match PTMOD1
PTPER Period Load
PTPER Buffer Update Disable (UDIS) Zero Match Period Match PTMOD1 PTMOD0
Clock Control
PTMR Clock PTEN
FOSC/4
Prescaler 1:1, 1:4, 1:16, 1:64 Zero Match
Postscaler 1:1-1:16 Interrupt Control PTIF
Period Match PTMOD1 PTMOD0
The PWM time base can be configured for four different modes of operation: * * * * Free-Running mode Single-Shot mode Continuous Up/Down Count mode Continuous Up/Down Count mode with interrupts for double updates
These four modes are selected by the PTMOD1:PTMOD0 bits in the PTCON0 register. The Free-Running mode produces edge-aligned PWM generation. The Continuous Up/Down Count modes produce center-aligned PWM generation. The SingleShot mode allows the PWM module to support pulse control of certain Electronically Commutated Motors (ECMs) and produces edge-aligned operation.
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REGISTER 14-1:
R/W-0 PTOPS3 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PTCON0: PWM TIMER CONTROL REGISTER 0
R/W-0 R/W-0 PTOPS1 R/W-0 PTOPS0 R/W-0 PTCKPS1 R/W-0 PTCKPS0 R/W-0 PTMOD1 R/W-0 PTMOD0 bit 0
PTOPS2
PTOPS3:PTOPS0: PWM Time Base Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale . . . 1111 = 1:16 Postscale PTCKPS1:PTCKPS0: PWM Time Base Input Clock Prescale Select bits 00 = PWM time base input clock is FOSC/4 (1:1 prescale) 01 = PWM time base input clock is FOSC/16 (1:4 prescale) 10 = PWM time base input clock is FOSC/64 (1:16 prescale) 11 = PWM time base input clock is FOSC/256 (1:64 prescale) PTMOD1:PTMOD0: PWM Time Base Mode Select bits 11 = PWM time base operates in a Continuous Up/Down Count mode with interrupts for double PWM updates 10 = PWM time base operates in a Continuous Up/Down Count mode 01 = PWM time base configured for Single-Shot mode 00 = PWM time base operates in a Free-Running mode
bit 3-2
bit 1-0
REGISTER 14-2:
R/W-0 PTEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PTCON1: PWM TIMER CONTROL REGISTER 1
R-0 PTDIR U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PTEN: PWM Time Base Timer Enable bit 1 = PWM time base is on 0 = PWM time base is off PTDIR: PWM Time Base Count Direction Status bit 1 = PWM time base counts down 0 = PWM time base counts up Unimplemented: Read as `0'
bit 6
bit 5-0
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REGISTER 14-3:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PWMCON0: PWM CONTROL REGISTER 0
R/W-1(1) PWMEN1 R/W-1(1) PWMEN0 U-0 -- R/W-0 PMOD2 R/W-0 PMOD1 R/W-0 PMOD0 bit 0
R/W-1(1) PWMEN2
Unimplemented: Read as `0' PWMEN2:PWMEN0: PWM Module Enable bits(1) 111 = All odd PWM I/O pins enabled for PWM output 110 = PWM1, PWM3 pins enabled for PWM output 10x = All PWM I/O pins enabled for PWM output 011 = PWM0, PWM1, PWM2 and PWM3 I/O pins enabled for PWM output 010 = PWM0 and PWM1 pins enabled for PWM output 001 = PWM1 pin is enabled for PWM output 000 = PWM module disabled; all PWM I/O pins are general purpose I/O Unimplemented: Read as `0' PMOD2:PMOD0: PWM Output Pair Mode bits For PMOD0: 1 = PWM I/O pin pair (PWM0, PWM1) is in the Independent mode 0 = PWM I/O pin pair (PWM0, PWM1) is in the Complementary mode For PMOD1: 1 = PWM I/O pin pair (PWM2, PWM3) is in the Independent mode 0 = PWM I/O pin pair (PWM2, PWM3) is in the Complementary mode For PMOD2: 1 = PWM I/O pin pair (PWM4, PWM5) is in the Independent mode 0 = PWM I/O pin pair (PWM4, PWM5) is in the Complementary mode Reset condition of PWMEN bits depends on the PWMPIN Configuration bit of CONFIG3L.
bit 3 bit 2-0
Note 1:
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REGISTER 14-4:
R/W-0 SEVOPS3 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PWMCON1: PWM CONTROL REGISTER 1
R/W-0 R/W-0 SEVOPS1 R/W-0 SEVOPS0 R/W-0 SEVTDIR U-0 -- R/W-0 UDIS R/W-0 OSYNC bit 0
SEVOPS2
SEVOPS3:SEVOPS0: PWM Special Event Trigger Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale . . . 1111 = 1:16 Postscale SEVTDIR: Special Event Trigger Time Base Direction bit 1 = A Special Event Trigger will occur when the PWM time base is counting downwards 0 = A Special Event Trigger will occur when the PWM time base is counting upwards Unimplemented: Read as `0' UDIS: PWM Update Disable bit 1 = Updates from Duty Cycle and Period Buffer registers are disabled 0 = Updates from Duty Cycle and Period Buffer registers are enabled OSYNC: PWM Output Override Synchronization bit 1 = Output overrides via the OVDCON register are synchronized to the PWM time base 0 = Output overrides via the OVDCON register are asynchronous
bit 3
bit 2 bit 1
bit 0
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14.3.1 FREE-RUNNING MODE
In the Free-Running mode, the PWM time base (PTMRL and PTMRH) will begin counting upwards until the value in the PWM Time Base Period register, PTPER (PTPERL and PTPERH), is matched. The PTMR registers will be reset on the following input clock edge and the time base will continue counting upwards as long as the PTEN bit remains set. Table 14-1 shows the minimum PWM frequencies that can be generated with the PWM time base and the prescaler. An operating frequency of 40 MHz (FCYC = 10 MHz) and PTPER = 0xFFF are assumed in the table. The PWM module must be capable of generating PWM signals at the line frequency (50 Hz or 60 Hz) for certain power control applications.
TABLE 14-1:
MINIMUM PWM FREQUENCY
14.3.2
SINGLE-SHOT MODE
In the Single-Shot mode, the PWM time base will begin counting upwards when the PTEN bit is set. When the value in the PTMR register matches the PTPER register, the PTMR register will be reset on the following input clock edge and the PTEN bit will be cleared by the hardware to halt the time base.
Minimum PWM Frequencies vs. Prescaler Value for FCYC = 10 MIPS (PTPER = 0FFFh) Prescale 1:1 1:4 1:16 1:64 PWM Frequency Edge-Aligned 2441 Hz 610 Hz 153 Hz 38 Hz PWM Frequency Center-Aligned 1221 Hz 305 Hz 76 Hz 19 Hz
14.3.3
CONTINUOUS UP/DOWN COUNT MODES
In Continuous Up/Down Count modes, the PWM time base counts upwards until the value in the PTPER register matches the PTMR register. On the following input clock edge, the timer counts downwards. The PTDIR bit in the PTCON1 register is read-only and indicates the counting direction. The PTDIR bit is set when the timer counts downwards. Note: Since the PWM compare outputs are driven to the active state when the PWM time-base is counting downwards and matches the duty cycle value, the PWM outputs are held inactive during the first half of the first period of the Continuous Up/Down Count mode until the PTMR begins to count down from the PTPER value.
14.3.5
PWM TIME BASE POSTSCALER
The match output of PTMR can optionally be postscaled through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate an interrupt. The postscaler counter is cleared when any of the following occurs: * Write to the PTMR register * Write to the PTCONx register * Any device Reset The PTMR register is not cleared when PTCONx is written.
14.4
PWM Time Base Interrupts
14.3.4
PWM TIME BASE PRESCALER
The input clock to PTMR (FOSC/4) has prescaler options of 1:1, 1:4, 1:16 or 1:64. These are selected by control bits, PTCKPS<1:0>, in the PTCON0 register. The prescaler counter is cleared when any of the following occurs: * Write to the PTMR register * Write to the PTCON (PTCON0 or PTCON1) register * Any device Reset Note: The PTMR register is not cleared when PTCONx is written.
The PWM timer can generate interrupts based on the modes of operation selected by the PTMOD<1:0> bits and the postscaler bits (PTOPS<3:0>).
14.4.1
INTERRUPTS IN FREE-RUNNING MODE
When the PWM time base is in the Free-Running mode (PTMOD<1:0> = 00), an interrupt event is generated each time a match with the PTPER register occurs. The PTMR register is reset to zero in the following clock edge. Using a postscaler selection other than 1:1 will reduce the frequency of interrupt events.
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FIGURE 14-5: PWM TIME BASE INTERRUPT TIMING, FREE-RUNNING MODE
A: PRESCALER = 1:1
Q1 FOSC/4 1 PTMR PTMR_INT_REQ FFEh FFFh 000h 001h 002h Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PTIF bit
B: PRESCALER = 1:4
Q4 Q4
Qc
Qc
Qc
Qc
Qc
Qc 1
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
PTMR PTMR_INT_REQ PTIF bit
FFEh
FFFh
000h
001h
002h
Note 1:
PWM Time Base Period register, PTPER, is loaded with the value FFFh for this example.
14.4.2
INTERRUPTS IN SINGLE-SHOT MODE
14.4.3
INTERRUPTS IN CONTINUOUS UP/DOWN COUNT MODE
When the PWM time base is in the Single-Shot mode (PTMOD<1:0> = 01), an interrupt event is generated when a match with the PTPER register occurs. The PWM Time Base register (PTMR) is reset to zero on the following input clock edge and the PTEN bit is cleared. The postscaler selection bits have no effect in this Timer mode.
In the Continuous Up/Down Count mode (PTMOD<1:0> = 10), an interrupt event is generated each time the value of the PTMR register becomes zero and the PWM time base begins to count upwards. The postscaler selection bits may be used in this Timer mode to reduce the frequency of the interrupt events. Figure 14-7 shows the interrupts in Continuous Up/ Down Count mode.
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FIGURE 14-6:
Q1 FOSC/4 2 PTMR 1 PTMR_INT_REQ FFEh 1 FFFh 1 000h 000h 000h
PWM TIME BASE INTERRUPT TIMING, SINGLE-SHOT MODE
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
A: PRESCALER = 1:1
PTIF bit
B: PRESCALER = 1:4
Qc Qc Qc Qc Qc Qc Qc Qc
Q4
Q4
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
2 PTMR 1 PTMR_INT_REQ FFEh 1 FFFh 1 000h 000h 000h
PTIF bit
Note 1: 2:
Interrupt flag bit, PTIF, is sampled here (every Q1). PWM Time Base Period register, PTPER, is loaded with the value FFFh for this example.
FIGURE 14-7:
PWM TIME BASE INTERRUPTS, CONTINUOUS UP/DOWN COUNT MODE
PRESCALER = 1:1
Q1 FOSC/4 PTMR PTDIR bit PTMR_INT_REQ 1 PTIF bit 1 1 1 002h 001h 000h 001h 002h Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PRESCALER = 1:4
Qc Qc Qc Qc Qc Qc Qc Qc
Q4
Q4
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
Qc
PTMR PTDIR bit 1 PTMR_INT_REQ
002h
001h
000h
001h
002h
1
1
1
PTIF bit
Note 1:
Interrupt flag bit, PTIF, is sampled here (every Q1).
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14.4.4 INTERRUPTS IN DOUBLE UPDATE MODE
2. This mode is available in Continuous Up/Down Count mode. In the Double Update mode (PTMOD<1:0> = 11), an interrupt event is generated each time the PTMR register is equal to zero and each time the PTMR matches the PTPER register. Figure 14-8 shows the interrupts in Continuous Up/Down Count mode with double updates. The Double Update mode provides two additional functions to the user in Center-Aligned mode. 1. The control loop bandwidth is doubled because the PWM duty cycles can be updated twice per period. Asymmetrical center-aligned PWM waveforms can be generated, which are useful for minimizing output waveform distortion in certain motor control applications. Note: Do not change the PTMOD bits while PTEN is active. It will yield unexpected results. To change the PWM Timer mode of operation, first clear the PTEN bit, load PTMOD bits with required data and then set PTEN.
FIGURE 14-8:
PWM TIME BASE INTERRUPTS, CONTINUOUS UP/DOWN COUNT MODE WITH DOUBLE UPDATES
A: PRESCALER = 1:1 Case 1: PTMR Counting Upwards
Q1 OSC1 2 PTMR 3FDh 3FEh 3FFh 3FEh 3FDh Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PTDIR bit
PTMR_INT_REQ 1 PTIF bit 1 1 1
Case 2: PTMR Counting Downwards
Q1 OSC1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PTMR PTDIR bit PTMR_INT_REQ 1 PTIF bit
002h
001h
000h
001h
002h
1 1 1
Note 1: 2:
Interrupt flag bit, PTIF, is sampled here (every Q1). PWM Time Base Period register, PTPER, is loaded with the value 3FFh for this example.
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14.5 PWM Period
The PWM period is defined by the PTPER register pair (PTPERL and PTPERH). The PWM period has 12-bit resolution by combining 4 LSBs of PTPERH and 8 bits of PTPERL. PTPER is a double-buffered register used to set the counting period for the PWM time base. The PTPER buffer contents are loaded into the PTPER register at the following times: * Free-Running and Single-Shot modes: When the PTMR register is reset to zero after a match with the PTPER register. * Continuous Up/Down Count modes: When the PTMR register is zero. The value held in the PTPER buffer is automatically loaded into the PTPER register when the PWM time base is disabled (PTEN = 0). Figure 14-9 and Figure 14-10 indicate the times when the contents of the PTPER buffer are loaded into the actual PTPER register. The PWM period can be calculated from the following formulas: The maximum resolution (in bits) for a given device oscillator and PWM frequency can be determined from the following formula:
EQUATION 14-4:
PWM RESOLUTION
log FOSC FPWM log(2)
Resolution =
The PWM resolutions and frequencies are shown for a selection of execution speeds and PTPER values in Table 14-2. The PWM frequencies in Table 14-2 are calculated for Edge-Aligned PWM mode. For CenterAligned mode, the PWM frequencies will be approximately one-half the values indicated in this table.
TABLE 14-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS
PWM Frequency = 1/TPWM FOSC 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 40 MHz 25 MHz 25 MHz 25 MHz 10 MHz 10 MHz 10 MHz 5 MHz 5 MHz 5 MHz 4 MHz 4 MHz 4 MHz Note: MIPS 10 10 10 10 10 10 10 10 10 6.25 6.25 6.25 2.5 2.5 2.5 1.25 1.25 1.25 1 1 1 PTPER PWM PWM Value Resolution Frequency 0FFFh 07FFh 03FFh 01FFh FFh 7Fh 3Fh 1Fh 0Fh 0FFFh 03FFh FFh 0FFFh 03FFh FFh 0FFFh 03FFh FFh 0FFFh 03FFh FFh 14 bits 13 bits 12 bits 11 bits 10 bits 9 bits 8 bits 7 bits 6 bits 14 bits 12 bits 10 bits 14 bits 12 bits 10 bits 14 bits 12 bits 10 bits 14 bits 12 bits 10 bits 2.4 kHz 4.9 kHz 9.8 kHz 19.5 kHz 39.0 kHz 78.1 kHz 156.2 kHz 312.5 kHz 625 kHz 1.5 kHz 6.1 kHz 24.4 kHz 610 Hz 2.4 kHz 9.8 kHz 305 Hz 1.2 kHz 4.9 kHz 244 Hz 976 Hz 3.9 kHz
EQUATION 14-1:
PWM PERIOD FOR FREE-RUNNING MODE
(PTPER + 1) x PTMRPS FOSC/4
TPWM =
EQUATION 14-2:
PWM PERIOD FOR CONTINUOUS UP/DOWN COUNT MODE
(2 x PTPER) x PTMRPS FOSC 4
TPWM =
The PWM frequency is the inverse of period; or
EQUATION 14-3:
PWM FREQUENCY
1 PWM Frequency = PWM Period
For center-aligned operation, PWM frequencies will be approximately 1/2 the value indicated in the table.
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FIGURE 14-9: PWM PERIOD BUFFER UPDATES IN FREE-RUNNING MODE
Period Value Loaded from PTPER Buffer Register
New PTPER Value = 007 5 Old PTPER Value = 004 3 2 1 0 0 1 2 0 4 3 1 4 3 2 4
7 6
New Value Written to PTPER Buffer
FIGURE 14-10:
PWM PERIOD BUFFER UPDATES IN CONTINUOUS UP/DOWN COUNT MODES
Period Value Loaded from PTPER Buffer Register
New PTPER Value = 007 6 5 Old PTPER Value = 004 3 2 1 0 4 3 2 1 0 1 2 3 4
7 6 5 4 3 2 1 0
New Value Written to PTPER Buffer
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14.6 PWM Duty Cycle
PWM duty cycle is defined by the PDCx (PDCxL and PDCxH) registers. There are a total of three PWM Duty Cycle registers for four pairs of PWM channels. The Duty Cycle registers have 14-bit resolution by combining the six LSbs of PDCxH with the 8 bits of PDCxL. PDCx is a double-buffered register used to set the counting period for the PWM time base. PTMR and the lower 2 bits are equal to Q1, Q2, Q3 or Q4, depending on the lower two bits of the PDCx (when the prescaler is 1:1 or PTCKPS<1:0> = 00). Note: When the prescaler is not 1:1 (PTCKPS<1:0> ~00), the duty cycle match occurs at the Q1 clock of the instruction cycle when the PTMR and PDCx match occurs.
14.6.1
PWM DUTY CYCLE REGISTERS
There are three 14-bit Special Function Registers used to specify duty cycle values for the PWM module: * PDC0 (PDC0L and PDC0H) * PDC1 (PDC1L and PDC1H) * PDC2 (PDC2L and PDC2H) The value in each Duty Cycle register determines the amount of time that the PWM output is in the active state. The upper 12 bits of PDCx hold the actual duty cycle value from PTMRH/L<11:0>, while the lower two bits control which internal Q clock the duty cycle match will occur. This 2-bit value is decoded from the Q clocks, as shown in Figure 14-11, when the prescaler is 1:1 (PTCKPS<1:0> = 00). In Edge-Aligned mode, the PWM period starts at Q1 and ends when the Duty Cycle register matches the PTMR register as follows. The duty cycle match is considered when the upper 12 bits of the PDCx are equal to the
Each compare unit has logic that allows override of the PWM signals. This logic also ensures that the PWM signals will complement each other (with dead-time insertion) in Complementary mode (see Section 14.7 "Dead-Time Generators"). Note: To get the correct PWM duty cycle, always multiply the calculated PWM duty cycle value by four before writing it to the PWM Duty Cycle registers. This is due to the two additional LSBs in the PWM Duty Cycle registers which are compared against the internal Q clock for the PWM duty cycle match.
FIGURE 14-11:
DUTY CYCLE COMPARISON
PTMRH<7:0> PTMRL<7:0>
PTMR<11:0> PTMRH<3:0> Unused Comparator Unused PDCxH<5:0> PDCx<13:0> PDCxH<7:0> Note 1: This value is decoded from the Q clocks: 00 = duty cycle match occurs on Q1 01 = duty cycle match occurs on Q2 10 = duty cycle match occurs on Q3 11 = duty cycle match occurs on Q4 PDCxL<7:0> PDCxL<7:0> PTMRL<7:0> Q Clocks(1) <1:0>
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14.6.2 DUTY CYCLE REGISTER BUFFERS 14.6.3 EDGE-ALIGNED PWM
The three PWM Duty Cycle registers are doublebuffered to allow glitchless updates of the PWM outputs. For each duty cycle block, there is a Duty Cycle Buffer register that is accessible by the user and a second Duty Cycle register that holds the actual compare value used in the present PWM period. In Edge-Aligned PWM Output mode, a new duty cycle value will be updated whenever a PTMR match with the PTPER register occurs and PTMR is reset, as shown in Figure 14-12. Also, the contents of the duty cycle buffers are automatically loaded into the Duty Cycle registers when the PWM time base is disabled (PTEN = 0). When the PWM time base is in the Continuous Up/ Down Count mode, new duty cycle values will be updated when the value of the PTMR register is zero and the PWM time base begins to count upwards. The contents of the duty cycle buffers are automatically loaded into the Duty Cycle registers when the PWM time base is disabled (PTEN = 0). Figure 14-13 shows the timings when the duty cycle update occurs for the Continuous Up/Down Count mode. In this mode, up to one entire PWM period is available for calculating and loading the new PWM duty cycle before changes take effect. When the PWM time base is in the Continuous Up/ Down Count mode with double updates, new duty cycle values will be updated when the value of the PTMR register is zero and when the value of the PTMR register matches the value in the PTPER register. The contents of the duty cycle buffers are automatically loaded into the Duty Cycle registers during both of the previously described conditions. Figure 14-14 shows the duty cycle updates for Continuous Up/Down Count mode with double updates. In this mode, up to half of a PWM period is available for calculating and loading the new PWM duty cycle before changes take effect. Edge-aligned PWM signals are produced by the module when the PWM time base is in the Free-Running mode or the Single-Shot mode. For edge-aligned PWM outputs, the output for a given PWM channel has a period specified by the value loaded in PTPER and a duty cycle specified by the appropriate Duty Cycle register (see Figure 14-12). The PWM output is driven active at the beginning of the period (PTMR = 0) and is driven inactive when the value in the Duty Cycle register matches PTMR. A new cycle is started when PTMR matches the PTPER, as explained in the PWM period section. If the value in a particular Duty Cycle register is zero, then the output on the corresponding PWM pin will be inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is greater than the value held in the PTPER register.
FIGURE 14-12:
EDGE-ALIGNED PWM
New Duty Cycle Latched
PTPER PDCx (old) PDCx (new) 0 Duty Cycle Active at Beginning of Period Period PTMR Value
FIGURE 14-13:
DUTY CYCLE UPDATE TIMES IN CONTINUOUS UP/DOWN COUNT MODE
Duty Cycle Value Loaded from Buffer Register
PWM Output
PTMR Value
New Value Written to Duty Cycle Buffer
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FIGURE 14-14: DUTY CYCLE UPDATE TIMES IN CONTINUOUS UP/DOWN COUNT MODE WITH DOUBLE UPDATES
Duty Cycle Value Loaded from Buffer Register
PWM Output
PTMR Value
New Values Written to Duty Cycle Buffer
14.6.4
CENTER-ALIGNED PWM
Center-aligned PWM signals are produced by the module when the PWM time base is configured in a Continuous Up/Down Count mode (see Figure 14-15). The PWM compare output is driven to the active state when the value of the Duty Cycle register matches the value of PTMR and the PWM time base is counting downwards (PTDIR = 1). The PWM compare output will be driven to the inactive state when the PWM time base is counting upwards (PTDIR = 0) and the value in the PTMR register matches the duty cycle value. If the value in a particular Duty Cycle register is zero, then the output on the corresponding PWM pin will be
inactive for the entire PWM period. In addition, the output on the PWM pin will be active for the entire PWM period if the value in the Duty Cycle register is equal to or greater than the value in the PTPER register. Note: When the PWM is started in CenterAligned mode, the PWM Time Base Period register (PTPER) is loaded into the PWM Time Base register (PTMR) and the PTMR is configured automatically to start down counting. This is done to ensure that all the PWM signals don't start at the same time.
FIGURE 14-15:
START OF CENTER-ALIGNED PWM
Period/2
PTPER Duty Cycle PTMR Value
0 Duty Cycle
Start of First PWM Period
Period
Period
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14.6.5 COMPLEMENTARY PWM OPERATION FIGURE 14-16:
The Complementary mode of PWM operation is useful to drive one or more power switches in half-bridge configuration, as shown in Figure 14-16. This inverter topology is typical for a 3-phase induction motor, brushless DC motor or 3-phase Uninterruptible Power Supply (UPS) control applications. Each upper/lower power switch pair is fed by a complementary PWM signal. Dead time may be optionally inserted during device switching, where both outputs are inactive for a short period (see Section 14.7 "Dead-Time Generators"). In Complementary mode, the duty cycle comparison units are assigned to the PWM outputs as follows: * PDC0 register controls PWM1/PWM0 outputs * PDC1 register controls PWM3/PWM2 outputs * PDC2 register controls PWM5/PWM4 outputs PWM1/3/5 are the main PWMs that are controlled by the PDCx registers and PWM0/2/4 are the complemented outputs. When using the PWMs to control the half-bridge, the odd number PWMs can be used to control the upper power switch and the even numbered PWMs can be used for the lower switches. The Complementary mode is selected for each PWM I/O pin pair by clearing the appropriate PMODx bit in the PWMCON0 register. The PWM I/O pins are set to Complementary mode by default upon all kinds of device Resets.
TYPICAL LOAD FOR COMPLEMENTARY PWM OUTPUTS
+V PWM1 PWM3 PWM5 3-Phase Load
PWM0
PWM2
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PWM4
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14.7 Dead-Time Generators
14.7.1 DEAD-TIME INSERTION
In power inverter applications, where the PWMs are used in Complementary mode to control the upper and lower switches of a half-bridge, a dead-time insertion is highly recommended. The dead-time insertion keeps both outputs in inactive state for a brief time. This avoids any overlap in the switching during the state change of the power devices due to TON and TOFF characteristics. Because the power output devices cannot switch instantaneously, some amount of time must be provided between the turn-off event of one PWM output in a complementary pair and the turn-on event of the other transistor. The PWM module allows dead time to be programmed. The following sections explain the dead-time block in detail. Each complementary output pair for the PWM module has a 6-bit down counter used to produce the deadtime insertion. As shown in Figure 14-17, each deadtime unit has a rising and falling edge detector connected to the duty cycle comparison output. The dead time is loaded into the timer on the detected PWM edge event. Depending on whether the edge is rising or falling, one of the transitions on the complementary outputs is delayed until the timer counts down to zero. A timing diagram, indicating the dead-time insertion for one pair of PWM outputs, is shown in Figure 14-18.
FIGURE 14-17:
Dead Time Select Bits
DEAD-TIME CONTROL UNIT BLOCK DIAGRAM FOR ONE PWM OUTPUT PAIR
Zero Compare
FOSC
Clock Control and Prescaler
6-Bit Down Counter Odd PWM Signal to Output Control Block Even PWM Signal to Output Control Block
Dead Time Prescale
Dead-Time Register
Duty Cycle Compare Input
FIGURE 14-18:
DEAD-TIME INSERTION FOR COMPLEMENTARY PWM
td PDC1 Compare Output PWM1 PWM0 td
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REGISTER 14-5:
R/W-0 DTPS1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
DTCON: DEAD-TIME CONTROL REGISTER
R/W-0 DTPS0 R/W-0 DT5 R/W-0 DT4 R/W-0 DT3 R/W-0 DT2 R/W-0 DT1 R/W-0 DT0 bit 0
DTPS1:DTPS0: Dead-Time Unit A Prescale Select bits 11 = Clock source for dead-time unit is FOSC/16 10 = Clock source for dead-time unit is FOSC/8 01 = Clock source for dead-time unit is FOSC/4 00 = Clock source for dead-time unit is FOSC/2 DT5:DT0: Unsigned 6-Bit Dead-Time Value for Dead-Time Unit bits
bit 5-0
14.7.2
DEAD-TIME RANGES
14.7.3
The amount of dead time provided by the dead-time unit is selected by specifying the input clock prescaler value and a 6-bit unsigned value defined in the DTCON register. Four input clock prescaler selections have been provided to allow a suitable range of dead times based on the device operating frequency. FOSC/2, FOSC/4, FOSC/8 and FOSC/16 are the clock prescaler options available using the DTPS1:DTPS0 control bits in the DTCON register. After selecting an appropriate prescaler value, the dead time is adjusted by loading a 6-bit unsigned value into DTCON<5:0>. The dead-time unit prescaler is cleared on any of the following events: * On a load of the down timer due to a duty cycle comparison edge event; * On a write to the DTCON register; or * On any device Reset.
DECREMENTING THE DEAD-TIME COUNTER
The dead-time counter is clocked from any of the Q clocks based on the following conditions. 1. The dead-time counter is clocked on Q1 when: * The DTPS bits are set to any of the following dead-time prescaler settings: FOSC/4, FOSC/8, FOSC/16 * The PWM Time Base Prescale bits (PTCKPS<1:0>) are set to any of the following prescale ratios: FOSC/16, FOSC/64, FOSC/256 The dead-time counter is clocked by a pair of Q clocks when the PWM Time Base Prescale bits are set to 1:1 (PTCKPS<1:0> = 00, FOSC/4) and the dead-time counter is clocked by the FOSC/2 (DTPS<1:0> = 00). The dead-time counter is clocked using every other Q clock, depending on the two LSbs in the Duty Cycle registers: * If the PWM duty cycle match occurs on Q1 or Q3, then the dead-time counter is clocked using every Q1 and Q3 * If the PWM duty cycles match occurs on Q2 or Q4, then the dead-time counter is clocked using every Q2 and Q4 When the DTPS<1:0> bits are set to any of the other dead-time prescaler settings (i.e., FOSC/4, FOSC/8 or FOSC/16) and the PWM time base prescaler is set to 1:1, the dead-time counter is clocked by the Q clock corresponding to the Q clocks on which the PWM duty cycle match occurs.
2.
3.
4.
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The actual dead time is calculated from the DTCON register as follows: Dead Time = Dead-Time Value/(FOSC/Prescaler) Table 14-3 shows example dead-time ranges as a function of the input clock prescaler selected and the device operating frequency.
14.7.4
DEAD-TIME DISTORTION
TABLE 14-3:
FOSC MIPS (MHz) 40 40 40 40 32 32 32 32 25 25 25 25 20 20 20 20 10 10 10 10 5 5 5 5 4 4 4 4 10 10 10 10 8 8 8 8 6.25 6.25 6.25 6.25 5 5 5 5 2.5 2.5 2.5 2.5 1.25 1.25 1.25 1.25 1 1 1 1
EXAMPLE DEAD-TIME RANGES
Prescaler Dead-Time Dead-Time Selection Min Max FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/2 FOSC/4 FOSC/8 FOSC/16 50 ns 100 ns 200 ns 400 ns 62.5 ns 125 ns 250 ns 500 ns 80 ns 160 ns 320 ns 640 ns 100 ns 200 ns 400 ns 800 ns 200 ns 400 ns 800 ns 1.6 s 400 ns 800 ns 1.6 s 3.2 s 0.5 s 1 s 2 s 4 s 3.2 s 6.4 s 12.8 s 25.6 s 4 s 8 s 16 s 32 s 5.12 s 10.2 s 20.5 s 41 s 6.4 s 12.8 s 25.6 s 51.2 s 12.8 s 25.6 s 51.2 s 102.4 s 25.6 s 51.2 s 102.4 s 204.8 s 32 s 64 s 128 s 256 s
Note 1: For small PWM duty cycles, the ratio of dead time to the active PWM time may become large. In this case, the inserted dead time will introduce distortion into waveforms produced by the PWM module. The user can ensure that dead-time distortion is minimized by keeping the PWM duty cycle at least three times larger than the dead time. A similar effect occurs for duty cycles at or near 100%. The maximum duty cycle used in the application should be chosen such that the minimum inactive time of the signal is at least three times larger than the dead time. If the dead time is greater or equal to the duty cycle of one of the PWM output pairs, then that PWM pair will be inactive for the whole period. 2: Changing the dead-time values in DTCON when the PWM is enabled may result in an undesirable situation. Disable the PWM (PTEN = 0) before changing the dead-time value.
14.8
Independent PWM Output
Independent PWM mode is used for driving the loads (as shown in Figure 14-19) that drive one winding of a switched reluctance motor. A particular PWM output pair is configured in the Independent Output mode when the corresponding PMODx bit in the PWMCON0 register is set. No dead-time control is implemented between the PWM I/O pins when the module is operating in the Independent PWM mode and both I/O pins are allowed to be active simultaneously. This mode can also be used to drive stepper motors.
14.8.1
DUTY CYCLE ASSIGNMENT IN THE INDEPENDENT PWM MODE
In the Independent PWM mode, each duty cycle generator is connected to both PWM output pins in a given PWM output pair. The odd and the even PWM output pins are driven with a single PWM duty cycle generator. PWM1 and PWM0 are driven by the PWM channel which uses the PDC0 register to set the duty cycle, PWM3 and PWM2 with PDC1, and PWM5 and PWM4 with PDC2 (see Figure 14-3 and Register 14-3).
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14.8.2 PWM CHANNEL OVERRIDE
PWM output may be manually overridden for each PWM channel by using the appropriate bits in the OVDCOND and OVDCONS registers. The user may select the following signal output options for each PWM output pin operating in the Independent PWM mode: * I/O pin outputs PWM signal * I/O pin inactive * I/O pin active Refer to Section 14.10 "PWM Output Override" for details for all the override functions. OVDCOND and OVDCONS registers are used to define the PWM override options. The OVDCOND register contains six bits, POVD5:POVD0, that determine which PWM I/O pins will be overridden. The OVDCONS register contains six bits, POUT5:POUT0, that determine the state of the PWM I/O pins when a particular output is overridden via the POVD bits. The POVD bits are active-low control bits. When the POVD bits are set, the corresponding POUT bit will have no effect on the PWM output. In other words, the pins corresponding to POVD bits that are set will have the duty PWM cycle set by the PDCx registers. When one of the POVD bits is cleared, the output on the corresponding PWM I/O pin will be determined by the state of the POUT bit. When a POUT bit is set, the PWM pin will be driven to its active state. When the POUT bit is cleared, the PWM pin will be driven to its inactive state.
FIGURE 14-19:
+V
CENTER CONNECTED LOAD
PWM1
Load
14.10.1
COMPLEMENTARY OUTPUT MODE
PWM0
14.9
Single-Pulse PWM Operation
The even numbered PWM I/O pins have override restrictions when a pair of PWM I/O pins are operating in the Complementary mode (PMODx = 0). In Complementary mode, if the even numbered pin is driven active by clearing the corresponding POVD bit and by setting the POUT bits in the OVDCOND and OVDCONS registers, the output signal is forced to be the complement of the odd numbered I/O pin in the pair (see Figure 14-2 for details).
The single-pulse PWM operation is available only in Edge-Aligned mode. In this mode, the PWM module will produce single-pulse output. Single-pulse operation is configured when the PTMOD1:PTMOD0 bits are set to `01' in the PTCON0 register. This mode of operation is useful for driving certain types of ECMs. In Single-Pulse mode, the PWM I/O pin(s) are driven to the active state when the PTEN bit is set. When the PWM timer match with Duty Cycle register occurs, the PWM I/O pin is driven to the inactive state. When the PWM timer match with the PTPER register occurs, the PTMR register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared and an interrupt is generated if the corresponding interrupt bit is set. Note: PTPER and PDCx values are held as they are after the single-pulse output. To have another cycle of single pulse, only PTEN has to be enabled.
14.10.2
OVERRIDE SYNCHRONIZATION
If the OSYNC bit in the PWMCON1 register is set, all output overrides performed via the OVDCOND and OVDCONS registers will be synchronized to the PWM time base. Synchronous output overrides will occur on the following conditions: * When the PWM is in Edge-Aligned mode, synchronization occurs when PTMR is zero. * When the PWM is in Center-Aligned mode, synchronization occurs when PTMR is zero and when the value of PTMR matches PTPER. Note 1: In the Complementary mode, the even channel cannot be forced active by a Fault or override event when the odd channel is active. The even channel is always the complement of the odd channel, with dead-time inserted, before the odd channel can be driven to its active state as shown in Figure 14-20. 2: Dead time inserted in the PWM channels even when they are in Override mode.
14.10 PWM Output Override
The PWM output override bits allow the user to manually drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units. The PWM override bits are useful when controlling various types of ECMs, like a BLDC motor.
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FIGURE 14-20: OVERRIDE BITS IN COMPLEMENTARY MODE
1
POUT0 POUT1
4 5
PWM1
2 7 3 6
PWM0
Assume: POVD0 = 0; POVD1 = 0; PMOD0 = 0 1. Even override bits have no effect in Complementary mode. 2. Odd override bit is activated which causes the even PWM to deactivate. 3. Dead-time insertion. 4. Odd PWM activated after the dead time. 5. Odd override bit is deactivated which causes the odd PWM to deactivate. 6. Dead-time insertion. 7. Even PWM is activated after the dead time.
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14.10.3 OUTPUT OVERRIDE EXAMPLES
Figure 14-21 shows an example of a waveform that might be generated using the PWM output override feature. The figure shows a six-step commutation sequence for a BLDC motor. The motor is driven through a 3-phase inverter as shown in Figure 14-16. When the appropriate rotor position is detected, the PWM outputs are switched to the next commutation state in the sequence. In this example, the PWM outputs are driven to specific logic states. The OVDCOND and OVDCONS register values used to generate the signals in Figure 14-21 are given in Table 14-4. The PWM Duty Cycle registers may be used in conjunction with the OVDCOND and OVDCONS registers. The Duty Cycle registers control the average voltage across the load and the OVDCOND and OVDCONS registers control the commutation sequence. Figure 14-22 shows the waveforms, while Table 14-4 and Table 14-5 show the OVDCOND and OVDCONS register values used to generate the signals.
REGISTER 14-6:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
OVDCOND: OUTPUT OVERRIDE CONTROL REGISTER
U-0 -- R/W-1 POVD5 R/W-1 POVD4 R/W-1 POVD3 R/W-1 POVD2 R/W-1 POVD1 R/W-1 POVD0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' POVD5:POVD0: PWM Output Override bits 1 = Output on PWM I/O pin is controlled by the value in the Duty Cycle register and the PWM time base 0 = Output on PWM I/O pin is controlled by the value in the corresponding POUTx bit
REGISTER 14-7:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-0
OVDCONS: OUTPUT STATE REGISTER
U-0 -- R/W-0 POUT5 R/W-0 POUT4 R/W-0 POUT3 R/W-0 POUT2 R/W-0 POUT1 R/W-0 POUT0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' POUT5:POUT0: PWM Manual Output bits(1) 1 = Output on PWM I/O pin is active when the corresponding PWM output override bit is cleared 0 = Output on PWM I/O pin is inactive when the corresponding PWM output override bit is cleared Note 1: With PWMs configured in complementary mode, even PWM (PWM0, 2, 4) outputs will be complementary of the odd PWM (PWM1, 3, 5) outputs, irrespective of the POUT bit setting.
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FIGURE 14-21: PWM OUTPUT OVERRIDE EXAMPLE #1
2 3 4 5 6
14.11 PWM Output and Polarity Control
There are three device Configuration bits associated with the PWM module that provide PWM output pin control defined in the CONFIG3L register. They are: * HPOL * LPOL * PWMPIN These three Configuration bits work in conjunction with the three PWM Enable bits (PWMEN2:PWMEN0) in the PWMCON0 register. The Configuration bits and PWM enable bits ensure that the PWM pins are in the correct states after a device Reset occurs.
1 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
TABLE 14-4:
State 1 2 3 4 5 6
PWM OUTPUT OVERRIDE EXAMPLE #1
OVDCONS (POUT) 00100100b 00100001b 00001001b 00011000b 00010010b 00000110b
14.11.1
OUTPUT PIN CONTROL
OVDCOND (POVD) 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b
The PWMEN2:PWMEN0 control bits enable each PWM output pin as required in the application. All PWM I/O pins are general purpose I/O. When a pair of pins is enabled for PWM output, the PORT and TRIS registers controlling the pins are disabled. Refer to Figure 14-23 for details.
14.11.2
OUTPUT POLARITY CONTROL
TABLE 14-5:
State 1 2 3 4
PWM OUTPUT OVERRIDE EXAMPLE #2
OVDCONS (POUT) 00000000b 00000000b 00000000b 00000000b
OVDCOND (POVD) 00000011b 00110000b 00111100b 00001111b
The polarity of the PWM I/O pins is set during device programming via the HPOL and LPOL Configuration bits in the CONFIG3L register. The HPOL Configuration bit sets the output polarity for the high side PWM outputs: PWM1, PWM3 and PWM5. The polarity is active-high when HPOL is set (= 1) and active-low when it is cleared (= 0). The LPOL Configuration bit sets the output polarity for the low side PWM outputs: PWM0, PWM2 and PWM4. As with HPOL, they are active-high when LPOL is set and active-low when cleared. All output signals generated by the PWM module are referenced to the polarity control bits, including those generated by Fault inputs or manual override (see Section 14.10 "PWM Output Override"). The default polarity Configuration bits have the PWM I/O pins in active-high output polarity.
FIGURE 14-22:
PWM OUTPUT OVERRIDE EXAMPLE #2
1 2 3 4
PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
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FIGURE 14-23: PWM I/O PIN BLOCK DIAGRAM
PWM Signal from Module
1
0
PWM Pin Enable Data Bus WR PORT
D CK Q Q
VDD P
Data Latch I/O pin N VSS
D
Q Q
WR TRIS
CK
TRIS Latch
RD TRIS
Q D EN
TTL or Schmitt Trigger
RD PORT
Note:
I/O pin has protection diodes to VDD and VSS. PWM polarity selection logic not shown for clarity.
14.11.3
PWM OUTPUT PIN RESET STATES
The PWMPIN Configuration bit determines the PWM output pins to be PWM output pins, or digital I/O pins, after the device comes out of Reset. If the PWMPIN Configuration bit is unprogrammed (default), the PWMEN2:PWMEN0 control bits will be cleared on a device Reset. Consequently, all PWM outputs will be tri-stated and controlled by the corresponding PORT and TRIS registers. If the PWMPIN Configuration bit is programmed low, the PWMEN2:PWMEN0 control bits will be set to `100' on a device Reset: All PWM pins will be enabled for PWM output and will have the output polarity defined by the HPOL and LPOL Configuration bits.
directly in hardware so that when a Fault occurs, it can be managed quickly and the PWMs outputs are put into an inactive state to save the power devices connected to the PWMs. The PWM Fault input is FLTA, which can come from I/O pins, the CPU or another module. The FLTA pin is an active-low input so it is easy to "OR" many sources to the same input. The FLTCONFIG register (Register 14-8) defines the settings of the FLTA input. Note: The inactive state of the PWM pins is dependent on the HPOL and LPOL Configuration bit settings, which define the active and inactive state for PWM outputs.
14.12 PWM Fault Input
There is one Fault input associated with the PWM module. The main purpose of the input Fault pin is to disable the PWM output signals and drive them into an inactive state. The action of the Fault input is performed
14.12.1
FAULT PIN ENABLE BIT
By setting the bit FLTAEN in the FLTCONFIG register, the corresponding Fault input is enabled. If FLTAEN bit is cleared, then the Fault input has no effect on the PWM module.
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14.12.2 FAULT INPUT MODE 14.12.3
The FLTAMOD bit in the FLTCONFIG register determines whether the PWM I/O pins are deactivated when they are overridden by a Fault input. FLTAS bit in the FLTCONFIG register gives the status of the Fault A input. The Fault input has two modes of operation: * Inactive Mode (FLTAMOD = 0) This is a catastrophic Fault Management mode. When the Fault occurs in this mode, the PWM outputs are deactivated. The PWM pins will remain in Inactivated mode until the Fault is cleared (Fault input is driven high) and the corresponding Fault status bit has been cleared in software. The PWM outputs are enabled immediately at the beginning of the following PWM period, after Fault status bit (FLTAS) is cleared. * Cycle-by-Cycle Mode (FLTAMOD = 1) When the Fault occurs in this mode, the PWM outputs are deactivated. The PWM outputs will remain in the defined Fault states (all PWM outputs inactive) for as long as the Fault pin is held low. After the Fault pin is driven high, the PWM outputs will return to normal operation at the beginning of the following PWM period and the FLTAS bit is automatically cleared.
PWM OUTPUTS WHILE IN FAULT CONDITION
While in the Fault state (i.e., FLTA input is active), the PWM output signals are driven into their inactive states.
14.12.4
PWM OUTPUTS IN DEBUG MODE
The BRFEN bit in the FLTCONFIG register controls the simulation of Fault condition when a breakpoint is hit, while debugging the application using an In-Circuit Debugger (ICD). Setting the BRFEN bit to high enables the Fault condition on breakpoint, thus driving the PWM outputs to inactive state. This is done to avoid any continuous keeping of status on the PWM pin, which may result in damage of the power devices connected to the PWM outputs. If BRFEN = 0, the Fault condition on breakpoint is disabled. Note: It is highly recommended to enable the Fault condition on breakpoint if a debugging tool is used while developing the firmware and the high-power circuitry is used. When the device is ready to program after debugging the firmware, the BRFEN bit can be disabled.
REGISTER 14-8:
R/W-0 BRFEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7
FLTCONFIG: FAULT CONFIGURATION REGISTER
U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 FLTAS R/W-0 FLTAMOD R/W-0 FLTAEN bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
BRFEN: Breakpoint Fault Enable bit 1 = Enable Fault condition on a breakpoint 0 = Disable Fault condition Unimplemented: Read as `0' FLTAS: Fault A Status bit 1 = FLTA is asserted: if FLTAMOD = 0, cleared by the user; if FLTAMOD = 1, cleared automatically at beginning of the new period when FLTA is deasserted 0 = No Fault FLTAMOD: Fault A Mode bit 1 = Cycle-by-Cycle mode: Pins are inactive for the remainder of the current PWM period or until FLTA is deasserted; FLTAS is cleared automatically 0 = Inactive mode: Pins are deactivated (catastrophic failure) until FLTA is deasserted and FLTAS is cleared by the user only FLTAEN: Fault A Enable bit 1 = Enable Fault A 0 = Disable Fault A
bit 6-3 bit 2
bit 1
bit 0
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14.13 PWM Update Lockout
For a complex PWM application, the user may need to write up to four Duty Cycle registers and the PWM Time Base Period Register, PTPER, at a given time. In some applications, it is important that all buffer registers be written before the new duty cycle and period values are loaded for use by the module. A PWM update lockout feature may optionally be enabled so the user may specify when new duty cycle buffer values are valid. The PWM update lockout feature is enabled by setting the control bit, UDIS, in the PWMCON1 register. This bit affects all Duty Cycle Buffer registers and the PWM Time Base Period register, PTPER. To perform a PWM update lockout: 1. 2. 3. 4. Set the UDIS bit. Write all Duty Cycle registers and PTPER, if applicable. Clear the UDIS bit to re-enable updates. With this, when UDIS bit is cleared, the buffer values will be loaded to the actual registers. This makes a synchronous loading of the registers. The PTMR value for which a Special Event Trigger should occur is loaded into the SEVTCMP register pair. SEVTDIR bit in PWMCON1 register specifies the counting phase when the PWM time base is in a Continuous Up/Down Count mode. If the SEVTDIR bit is cleared, the Special Event Trigger will occur on the upward counting cycle of the PWM time base. If SEVTDIR is set, the Special Event Trigger will occur on the downward count cycle of the PWM time base. The SEVTDIR bit only effects this operation when the PWM timer is in the Continuous Up/Down Count mode. Note: The Special Event Trigger will take place only for non-zero values in the SEVTCMP registers.
14.14.1
SPECIAL EVENT TRIGGER ENABLE
The PWM module will always produce Special Event Trigger pulses. This signal may optionally be used by the A/D module. Refer to Chapter 16.0 "10-Bit Analog-to-Digital Converter (A/D) Module" for details.
14.14.2
14.14 PWM Special Event Trigger
The PWM module has a Special Event Trigger capability that allows A/D conversions to be synchronized to the PWM time base. The A/D sampling and conversion time may be programmed to occur at any point within the PWM period. The Special Event Trigger allows the user to minimize the delay between the time when A/D conversion results are acquired and the time when the duty cycle value is updated. The PWM 16-bit Special Event Trigger register, SEVTCMP (high and low), and five control bits in the PWMCON1 register are used to control its operation.
SPECIAL EVENT TRIGGER POSTSCALER
The PWM Special Event Trigger has a postscaler that allows a 1:1 to 1:16 postscale ratio. The postscaler is configured by writing the SEVOPS3:SEVOPS0 control bits in the PWMCON1 register. The Special Event Trigger output postscaler is cleared on any write to the SEVTCMP register pair, or on any device Reset.
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TABLE 14-6:
Name INTCON IPR3 PIE3 PIR3 PTCON0 PTCON1 PTMRL(1) PTMRH(1) PTPERL(1) PTPERH(1)
REGISTERS ASSOCIATED WITH THE POWER CONTROL PWM MODULE
Bit 7 Bit 6 Bit 5 TMR0IE -- -- -- PTOPS1 -- -- -- Bit 4 INT0IE PTIP PTIE PTIF PTOPS0 -- -- -- Bit 3 RBIE -- -- -- Bit 2 TMR0IF -- -- -- Bit 1 INT0IF -- -- -- Bit 0 RBIF -- -- -- Reset Values on Page: 47 49 49 49 49 49 49 PWM Time Base Register (upper 4 bits) PWM Time Base Period Register (upper 4 bits) PWM Special Event Compare Register (upper 4 bits) -- SEVTDIR DT3 -- POVD3 POUT3 PMOD2 -- DT2 FLTAS POVD2 POUT2 PMOD1 UDIS DT1 POVD1 POUT1 PMOD0 OSYNC DT0 POVD0 POUT0 49 49 49 49 50 50 50 50 49 50 50 49 49 49 49 49 49
GIE/GIEH PEIE/GIEL -- -- -- PTOPS3 PTEN -- -- -- -- -- PTOPS2 PTDIR -- --
PTCKPS1 PTCKPS 0 -- --
PTMOD1 PTMOD0 -- --
PWM Time Base Register (lower 8 bits) PWM Time Base Period Register (lower 8 bits)
SEVTCMPL(1) PWM Special Event Compare Register (lower 8 bits) SEVTCMPH(1) PWMCON0 PWMCON1 DTCON FLTCONFIG OVDCOND OVDCONS PDC0L(1) PDC0H(1) PDC1L(1) PDC1H(1) PDC2L
(1)
-- -- DTPS1 BRFEN -- -- -- -- --
--
--
--
PWMEN2(2) PWMEN1(2) PWMEN0(2) SEVOPS1 DT5 -- POVD5 POUT5 SEVOPS0 DT4 -- POVD4 POUT4 DTPS0 -- -- -- -- -- --
SEVOPS3 SEVOPS2
FLTAMOD FLTAEN
PWM Duty Cycle #0L Register (lower 8 bits) PWM Duty Cycle #0H Register (upper 6 bits) PWM Duty Cycle #1H Register (upper 6 bits) PWM Duty Cycle #2H Register (upper 6 bits) PWM Duty Cycle #1L Register (lower 8 bits) PWM Duty Cycle #2L Register (lower 8 bits) -- = unimplemented, read as `0'. Shaded cells are not used with the Power Control PWM. Double-buffered register pairs. Refer to text for explanation of how these registers are read and written to. Reset condition of PWMEN bits depends on the PWMPIN Configuration bit.
PDC2H(1) Legend: Note 1: 2:
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NOTES:
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15.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART)
The pins of the Enhanced USART are multiplexed with PORTA. In order to configure RA2/TX/CK and RA3/RX/DT as an EUSART: * bit SPEN (RCSTA<7>) must be set (= 1) * bit TRISA<3> must be set (= 1) * bit TRISA<2> must be set (= 1) Note: The EUSART control will automatically reconfigure the pin from input to output as needed.
The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is one of the two serial I/O modules. (Generically, the USART is also known as a Serial Communications Interface or SCI.) The EUSART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers. It can also be configured as a halfduplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc. The Enhanced USART module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on Sync Break reception and 12-bit Break character transmit. These features make it ideally suited for use in Local Interconnect Network bus (LIN/J2602 bus) systems. The EUSART can be configured in the following modes: * Asynchronous (full-duplex) with: - Auto-Wake-up on Character Reception - Auto-Baud Calibration - 12-Bit Break Character Transmission * Synchronous - Master (half-duplex) with Selectable Clock Polarity * Synchronous - Slave (half-duplex) with Selectable Clock Polarity
The operation of the Enhanced USART module is controlled through three registers: * Transmit Status and Control (TXSTA) * Receive Status and Control (RCSTA) * Baud Rate Control (BAUDCON) These are detailed on the following pages in Register 15-1, Register 15-2 and Register 15-3, respectively.
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REGISTER 15-1:
R/W-0 CSRC bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
R/W-0 TX9 R/W-0 TXEN
(1)
R/W-0 SYNC
R/W-0 SENDB
R/W-0 BRGH
R-1 TRMT
R/W-0 TX9D bit 0
CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-Bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don't care. BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode. TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data Can be address/data bit or a parity bit. SREN/CREN overrides TXEN in Sync mode.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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REGISTER 15-2:
R/W-0 SPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RCSTA: RECEIVE STATUS AND CONTROL REGISTER
R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0
SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and loads the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 9-bit (RX9 = 0): Don't care. FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receiving next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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REGISTER 15-3:
R/W-0 ABDOVF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
BAUDCON: BAUD RATE CONTROL REGISTER
R-1 RCIDL R/W-0 RXDTP R/W-0 TXCKP R/W-0 BRG16 U-0 -- R/W-0 WUE R/W-0 ABDEN bit 0
ABDOVF: Auto-Baud Acquisition Rollover Status bit 1 = A BRG rollover has occurred during Auto-Baud Rate Detect mode (must be cleared in software) 0 = No BRG rollover has occurred RCIDL: Receive Operation Idle Status bit 1 = Receive operation is Idle 0 = Receive operation is active RXDTP: Received Data Polarity Select bit Asynchronous mode: 1 = RX data is inverted 0 = RX data is not inverted Synchronous mode: Unused in this mode. TXCKP: Clock and Data Polarity Select bit Asynchronous mode: 1 = Idle state for transmit (TX) is a low level 0 = Idle state for transmit (TX) is a high level Synchronous mode: 1 = Idle state for clock (CK) is a high level 0 = Idle state for clock (CK) is a low level BRG16: 16-Bit Baud Rate Register Enable bit 1 = 16-bit Baud Rate Generator - SPBRGH and SPBRG 0 = 8-bit Baud Rate Generator - SPBRG only (Compatible mode), SPBRGH value ignored Unimplemented: Read as `0' WUE: Wake-up Enable bit Asynchronous mode: 1 = EUSART will continue to sample the RX pin - interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = RX pin not monitored or rising edge detected Synchronous mode: Unused in this mode. ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Synchronous mode: Unused in this mode.
bit 6
bit 5
bit 4
bit 3
bit 2 bit 1
bit 0
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15.1 Baud Rate Generator (BRG)
The BRG is a dedicated 8-bit or 16-bit generator that supports both the Asynchronous and Synchronous modes of the EUSART. By default, the BRG operates in 8-bit mode; setting the BRG16 bit (BAUDCON<3>) selects 16-bit mode. The SPBRGH:SPBRG register pair controls the period of a free-running timer. In Asynchronous mode, bits BRGH (TXSTA<2>) and BRG16 (BAUDCON<3>) also control the baud rate. In Synchronous mode, BRGH is ignored. Table 15-1 shows the formula for computation of the baud rate for different EUSART modes which only apply in Master mode (internally generated clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRGH:SPBRG registers can be calculated using the formulas in Table 15-1. From this, the error in baud rate can be determined. An example calculation is shown in Example 15-1. Typical baud rates and error values for the various Asynchronous modes are shown in Table 15-2. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. Writing a new value to the SPBRGH:SPBRG registers causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. Note: A BRG value of `0' is not supported.
15.1.1
OPERATION IN POWER-MANAGED MODES
The device clock is used to generate the desired baud rate. When one of the power-managed modes is entered, the new clock source may be operating at a different frequency. This may require an adjustment to the value in the SPBRG register pair.
15.1.2
SAMPLING
The data on the RX pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin when SYNC is clear or when both BRG16 and BRGH are not set. The data on the RX pin is sampled once when SYNC is set or when BRGH16 and BRGH are both set.
TABLE 15-1:
SYNC 0 0 0 0 1 1
BAUD RATE FORMULAS
BRG16 0 0 1 1 0 1 BRGH 0 1 0 1 x x BRG/EUSART Mode 8-bit/Asynchronous 8-bit/Asynchronous 16-bit/Asynchronous 16-bit/Asynchronous 8-bit/Synchronous 16-bit/Synchronous FOSC/[4 (n + 1)] Baud Rate Formula FOSC/[64 (n + 1)] FOSC/[16 (n + 1)]
Configuration Bits
Legend: x = Don't care, n = value of SPBRGH:SPBRG register pair
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EXAMPLE 15-1: CALCULATING BAUD RATE ERROR
For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: Desired Baud Rate = FOSC/(64 ([SPBRGH:SPBRG] + 1)) Solving for SPBRGH:SPBRG: X = ((FOSC/Desired Baud Rate)/64) - 1 = ((16000000/9600)/64) - 1 = [25.042] = 25 Calculated Baud Rate = 16000000/(64 (25 + 1)) = 9615 Error = (Calculated Baud Rate - Desired Baud Rate)/Desired Baud Rate = (9615 - 9600)/9600 = 0.16%
TABLE 15-2:
Name TXSTA RCSTA SPBRGH SPBRG
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7 CSRC SPEN Bit 6 TX9 RX9 RCIDL Bit 5 TXEN SREN RXDTP Bit 4 SYNC CREN TXCKP Bit 3 SENDB ADDEN BRG16 Bit 2 BRGH FERR -- Bit 1 TRMT OERR WUE Bit 0 TX9D RX9D ABDEN Reset Values on Page: 48 48 48 48 48
BAUDCON ABDOVF
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the BRG.
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TABLE 15-3:
BAUD RATE (K)
BAUD RATES FOR ASYNCHRONOUS MODES
SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 20.000 MHz Actual Rate (K) -- 1.221 2.404 9.766 19.531 62.500 104.167 % Error -- 1.73 0.16 1.73 1.73 8.51 -9.58 SPBRG value
(decimal)
FOSC = 40.000 MHz Actual Rate (K) -- -- 2.441 9.615 19.531 56.818 125.000 % Error -- -- 1.73 0.16 1.73 -1.36 8.51 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) -- 1.202 2.404 9.766 19.531 52.083 78.125 % Error -- 0.16 0.16 1.73 1.73 -9.58 -32.18 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) -- 1.201 2.403 9.615 -- -- -- % Error -- -0.16 -0.16 -0.16 -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
-- -- 255 64 31 10 4
-- 255 129 31 15 4 2
-- 129 64 15 7 2 1
-- 103 51 12 -- -- --
SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.202 2.404 8.929 20.833 62.500 62.500 % Error 0.16 0.16 0.16 -6.99 8.51 8.51 -45.75 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) 0.300 1.201 2.403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 -- -- -- -- -- % Error -0.16 -0.16 -- -- -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
207 51 25 6 2 0 0
103 25 12 -- -- -- --
51 12 -- -- -- -- --
SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) -- -- -- 9.766 19.231 58.140 113.636 % Error -- -- -- 1.73 0.16 0.94 -1.36 SPBRG value
(decimal)
FOSC = 20.000 MHz Actual Rate (K) -- -- -- 9.615 19.231 56.818 113.636 % Error -- -- -- 0.16 0.16 -1.36 -1.36 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) -- -- 2.441 9.615 19.531 56.818 125.000 % Error -- -- 1.73 0.16 1.73 -1.36 8.51 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) -- -- 2.403 9.615 19.230 55.555 -- % Error -- -- -0.16 -0.16 -0.16 3.55 -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
-- -- -- 255 129 42 21
-- -- -- 129 64 21 10
-- -- 255 64 31 10 4
-- -- 207 51 25 8 --
SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) -- 1.202 2.404 9.615 19.231 62.500 125.000 % Error -- 0.16 0.16 0.16 0.16 8.51 8.51 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) -- 1.201 2.403 9.615 -- -- -- % Error -- -0.16 -0.16 -0.16 -- -- -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 2.403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
-- 207 103 25 12 3 1
-- 103 51 12 -- -- --
207 51 25 -- -- -- --
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TABLE 15-3:
BAUD RATE (K)
BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED)
SYNC = 0, BRGH = 0, BRG16 = 1 FOSC = 20.000 MHz Actual Rate (K) 0.300 1.200 2.399 9.615 19.231 56.818 113.636 % Error 0.02 -0.03 -0.03 0.16 0.16 -1.36 -1.36 SPBRG value
(decimal)
FOSC = 40.000 MHz Actual Rate (K) 0.300 1.200 2.402 9.615 19.231 58.140 113.636 % Error 0.00 0.02 0.06 0.16 0.16 0.94 -1.36 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) 0.300 1.200 2.404 9.615 19.531 56.818 125.000 % Error 0.02 -0.03 0.16 0.16 1.73 -1.36 8.51 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 19.230 55.555 -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 3.55 -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
8332 2082 1040 259 129 42 21
4165 1041 520 129 64 21 10
2082 520 259 64 31 10 4
1665 415 207 51 25 8 --
SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.202 2.404 9.615 19.231 62.500 125.000 % Error 0.04 0.16 0.16 0.16 0.16 8.51 8.51 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 -- -- -- % Error -0.16 -0.16 -0.16 -0.16 -- -- -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 2.403 -- -- -- -- % Error -0.16 -0.16 -0.16 -- -- -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
832 207 103 25 12 3 1
415 103 51 12 -- -- --
207 51 25 -- -- -- --
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 40.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.606 19.193 57.803 114.943 % Error 0.00 0.00 0.02 0.06 -0.03 0.35 -0.22 SPBRG value
(decimal)
FOSC = 20.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.596 19.231 57.471 116.279 % Error 0.00 0.02 0.02 -0.03 0.16 -0.22 0.94 SPBRG value
(decimal)
FOSC = 10.000 MHz Actual Rate (K) 0.300 1.200 2.402 9.615 19.231 58.140 113.636 % Error 0.00 0.02 0.06 0.16 0.16 0.94 -1.36 SPBRG value
(decimal)
FOSC = 8.000 MHz Actual Rate (K) 0.300 1.200 2.400 9.615 19.230 57.142 117.647 % Error -0.01 -0.04 -0.04 -0.16 -0.16 0.79 -2.12 SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
33332 8332 4165 1040 520 172 86
16665 4165 2082 520 259 86 42
8332 2082 1040 259 129 42 21
6665 1665 832 207 103 34 16
SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE (K) FOSC = 4.000 MHz Actual Rate (K) 0.300 1.200 2.404 9.615 19.231 58.824 111.111 % Error 0.01 0.04 0.16 0.16 0.16 2.12 -3.55 SPBRG value
(decimal)
FOSC = 2.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 19.230 55.555 -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 3.55 -- SPBRG value
(decimal)
FOSC = 1.000 MHz Actual Rate (K) 0.300 1.201 2.403 9.615 19.230 -- -- % Error -0.04 -0.16 -0.16 -0.16 -0.16 -- -- SPBRG value
(decimal)
0.3 1.2 2.4 9.6 19.2 57.6 115.2
3332 832 415 103 51 16 8
1665 415 207 51 25 8 --
832 207 103 25 12 -- --
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15.1.3 AUTO-BAUD RATE DETECT
The Enhanced USART module supports the automatic detection and calibration of baud rate. This feature is active only in Asynchronous mode and while the WUE bit is clear. The automatic baud rate measurement sequence (Figure 15-1) begins whenever a Start bit is received and the ABDEN bit is set. The calculation is self-averaging. In the Auto-Baud Rate Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. In ABD mode, the internal Baud Rate Generator is used as a counter to time the bit period of the incoming serial byte stream. Once the ABDEN bit is set, the state machine will clear the BRG and look for a Start bit. The Auto-Baud Rate Detect must receive a byte with the value 55h (ASCII "U", which is also the LIN/J2602 bus Sync character) in order to calculate the proper bit rate. The measurement is taken over both a low and a high bit time in order to minimize any effects caused by asymmetry of the incoming signal. After a Start bit, the SPBRG begins counting up, using the preselected clock source on the first rising edge of RX. After eight bits on the RX pin or the fifth rising edge, an accumulated value totalling the proper BRG period is left in the SPBRGH:SPBRG register pair. Once the 5th edge is seen (this should correspond to the Stop bit), the ABDEN bit is automatically cleared. If a rollover of the BRG occurs (an overflow from FFFFh to 0000h), the event is trapped by the ABDOVF status bit (BAUDCON<7>). It is set in hardware by BRG rollovers and can be set or cleared by the user in software. ABD mode remains active after rollover events and the ABDEN bit remains set (Figure 15-2). While calibrating the baud rate period, the BRG registers are clocked at 1/8th the preconfigured clock rate. Note that the BRG clock can be configured by the BRG16 and BRGH bits. The BRG16 bit must be set to use both SPBRG1 and SPBRGH1 as a 16-bit counter. This allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the SPBRGH register. Refer to Table 15-4 for counter clock rates to the BRG. While the ABD sequence takes place, the EUSART state machine is held in Idle. The RCIF interrupt is set once the fifth rising edge on RX is detected. The value in the RCREG needs to be read to clear the RCIF interrupt. The contents of RCREG should be discarded. Note 1: If the WUE bit is set with the ABDEN bit, Auto-Baud Rate Detection will occur on the byte following the Break character. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible due to bit error rates. Overall system timing and communication baud rates must be taken into consideration when using the Auto-Baud Rate Detection feature. 3: To maximize baud rate range, it is recommended to set the BRG16 bit if the autobaud feature is used.
TABLE 15-4:
BRG16 0 0 1 1 BRGH 0 1 0 1
BRG COUNTER CLOCK RATES
BRG Counter Clock FOSC/512 FOSC/128 FOSC/128 FOSC/32
15.1.3.1
ABD and EUSART Transmission
Since the BRG clock is reversed during ABD acquisition, the EUSART transmitter cannot be used during ABD. This means that whenever the ABDEN bit is set, TXREG cannot be written to. Users should also ensure that ABDEN does not become set during a transmit sequence. Failing to do this may result in unpredictable EUSART operation.
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FIGURE 15-1:
BRG Value RX pin
AUTOMATIC BAUD RATE CALCULATION
XXXXh 0000h Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 001Ch Edge #5 Stop bit
BRG Clock Set by User ABDEN bit RCIF bit (interrupt) Read RCREG SPBRG SPBRGH XXXXh XXXXh 1Ch 00h Auto-Cleared
Note: The ABD sequence requires the EUSART module to be configured in Asynchronous mode and WUE = 0.
FIGURE 15-2:
BRG Clock ABDEN bit RX pin ABDOVF bit
BRG OVERFLOW SEQUENCE
Start
bit 0
FFFFh BRG Value XXXXh 0000h 0000h
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15.2 EUSART Asynchronous Mode
15.2.1
The Asynchronous mode of operation is selected by clearing the SYNC bit (TXSTA<4>). In this mode, the EUSART uses standard Non-Return-to-Zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8 bits. An on-chip dedicated 8-bit/16-bit Baud Rate Generator can be used to derive standard baud rate frequencies from the oscillator. The EUSART transmits and receives the LSb first. The EUSART's transmitter and receiver are functionally independent but use the same data format and baud rate. The Baud Rate Generator produces a clock, either x16 or x64 of the bit shift rate depending on the BRGH and BRG16 bits (TXSTA<2> and BAUDCON<3>). Parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. In Asynchronous mode, clock polarity is selected with the TXCKP bit (BAUDCON<4>). Setting TXCKP sets the Idle state on CK as high, while clearing the bit sets the Idle state as low. Data polarity is selected with the RXDTP bit (BAUDCON<5>). Setting RXDTP inverts data on RX, while clearing the bit has no affect on received data. When operating in Asynchronous mode, the EUSART module consists of the following important elements: * * * * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver Auto-Wake-up on Sync Break Character 12-Bit Break Character Transmit Auto-Baud Rate Detection
EUSART ASYNCHRONOUS TRANSMITTER
The EUSART transmitter block diagram is shown in Figure 15-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and the TXIF flag bit (PIR1<4>) is set. This interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF will be set regardless of the state of TXIE; it cannot be cleared in software. TXIF is also not cleared immediately upon loading TXREG but becomes valid in the second instruction cycle following the load instruction. Polling TXIF immediately following a load of TXREG will return invalid results. While TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR register is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. To set up an Asynchronous Transmission: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
2. 3. 4. 5. 6. 7. 8.
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FIGURE 15-3: EUSART TRANSMIT BLOCK DIAGRAM
Data Bus TXIF TXIE MSb (8) Interrupt TXEN Baud Rate CLK TRMT BRG16 SPBRGH SPBRG TX9 TX9D SPEN TSR Register TXREG Register 8 LSb 0 Pin Buffer and Control TX pin
Baud Rate Generator
FIGURE 15-4:
Write to TXREG BRG Output (Shift Clock) TX (pin) TXIF bit (Transmit Buffer Reg. Empty Flag)
ASYNCHRONOUS TRANSMISSION
Word 1
Start bit 1 TCY
bit 0
bit 1 Word 1
bit 7/8
Stop bit
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
FIGURE 15-5:
Write to TXREG
ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
Word 1 Word 2
BRG Output (Shift Clock) TX (pin) TXIF bit (Interrupt Reg. Flag) 1 TCY 1 TCY Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Start bit bit 0 bit 1 Word 1 bit 7/8 Stop bit Start bit Word 2 bit 0
TRMT bit (Transmit Shift Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
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TABLE 15-5:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA BAUDCON SPBRGH SPBRG
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN RXDTP Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC TXCKP Bit 3 RBIE CMP2IF CMP2IE CMP2IP ADDEN SENDB BRG16 Bit 2 TMR0IF CMP1IF CMP1IE CMP1IP FERR BRGH -- Bit 1 INT0IF CMP0IF CMP0IE CMP0IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on Page: 47 49 49 49 48 48 48 48 48 48
GIE/GIEH PEIE/GIEL -- -- -- SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission.
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15.2.2 EUSART ASYNCHRONOUS RECEIVER 15.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT
The receiver block diagram is shown in Figure 15-6. The data is received on the RX pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. To set up an Asynchronous Reception: Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. 3. If interrupts are desired, set enable bit RCIE. 4. If 9-bit reception is desired, set bit RX9. 5. Enable the reception by setting bit CREN. 6. Flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if enable bit, RCIE, was set. 7. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. 1. This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be Acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU.
FIGURE 15-6:
EUSART RECEIVE BLOCK DIAGRAM
CREN x64 Baud Rate CLK OERR FERR
BRG16
SPBRGH
SPBRG
64 or 16 or 4
MSb Stop (8) 7
RSR Register 1 0
LSb Start
Baud Rate Generator RX9 Pin Buffer and Control RX Data Recovery RX9D RCREG Register FIFO
SPEN 8 Interrupt RCIF RCIE Data Bus
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PIC18F1230/1330
FIGURE 15-7:
RX (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set.
ASYNCHRONOUS RECEPTION
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit
Word 1 RCREG
Word 2 RCREG
Note:
TABLE 15-6:
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA BAUDCON SPBRGH SPBRG
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN RXDTP Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC TXCKP Bit 3 RBIE CMP2IF CMP2IE CMP2IP ADDEN SENDB BRG16 Bit 2 TMR0IF CMP1IF CMP1IE CMP1IP FERR BRGH -- Bit 1 INT0IF CMP0IF CMP0IE CMP0IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on Page: 47 49 49 49 48 48 48 48 48 48
GIE/GIEH PEIE/GIEL -- -- -- SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception.
15.2.4
AUTO-WAKE-UP ON SYNC BREAK CHARACTER
During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper byte reception cannot be performed. The auto-wake-up feature allows the controller to wake-up due to activity on the RX/DT line while the EUSART is operating in Asynchronous mode. The auto-wake-up feature is enabled by setting the WUE bit (BAUDCON<1>). Once set, the typical receive sequence on RX/DT is disabled and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a Wake-up Signal character for the LIN/J2602 protocol.)
Following a wake-up event, the module generates an RCIF interrupt. The interrupt is generated synchronously to the Q clocks in normal operating modes (Figure 15-8) and asynchronously if the device is in Sleep mode (Figure 15-9). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared once a low-tohigh transition is observed on the RX line following the wake-up event. At this point, the EUSART module is in Idle mode and returns to normal operation. This signals to the user that the Sync Break event is over.
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15.2.4.1 Special Considerations Using Auto-Wake-up 15.2.4.2 Special Considerations Using the WUE Bit
Since auto-wake-up functions by sensing rising edge transitions on RX/DT, information with any state changes before the Stop bit may signal a false End-of-Character and cause data or framing errors. To work properly, therefore, the initial characters in the transmission must be all `0's. This can be 00h (8 bits) for standard RS-232 devices or 000h (12 bits) for LIN/J2602 bus. Oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., XT or HS mode). The Sync Break (or Wake-up Signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. The timing of WUE and RCIF events may cause some confusion when it comes to determining the validity of received data. As noted, setting the WUE bit places the EUSART in an Idle mode. The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared after this when a rising edge is seen on RX/DT. The interrupt condition is then cleared by reading the RCREG register. Ordinarily, the data in RCREG will be dummy data and should be discarded. The fact that the WUE bit has been cleared (or is still set) and the RCIF flag is set should not be used as an indicator of the integrity of the data in RCREG. Users should consider implementing a parallel method in firmware to verify received data integrity. To assure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode.
FIGURE 15-8:
OSC1 WUE bit(1) RX/DT Line RCIF
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING NORMAL OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit Set by User
Auto-Cleared
Cleared Due to User Read of RCREG
Note 1: The EUSART remains in Idle while the WUE bit is set.
FIGURE 15-9:
OSC1 WUE bit(2) RX/DT Line RCIF
AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Bit Set by User
Auto-Cleared
Note 1 Sleep Ends Cleared Due to User Read of RCREG
Sleep Command Executed
Note 1: 2:
If the wake-up event requires long oscillator warm-up time, the auto-clear of the WUE bit can occur before the oscillator is ready. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set.
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15.2.5 BREAK CHARACTER SEQUENCE
3. 4. 5. The EUSART module has the capability of sending the special Break character sequences that are required by the LIN/J2602 bus standard. The Break character transmit consists of a Start bit, followed by twelve `0' bits and a Stop bit. The Frame Break character is sent whenever the SENDB and TXEN bits (TXSTA<3> and TXSTA<5>) are set while the Transmit Shift register is loaded with data. Note that the value of data written to TXREG will be ignored and all `0's will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN/J2602 specification). Note that the data value written to the TXREG for the Break character is ignored. The write simply serves the purpose of initiating the proper sequence. The TRMT bit indicates when the transmit operation is active or Idle, just as it does during normal transmission. See Figure 15-10 for the timing of the Break character sequence. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write `55h' to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware. The Sync character now transmits in the preconfigured mode.
When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG.
15.2.6
RECEIVING A BREAK CHARACTER
The Enhanced USART module can receive a Break character in two ways. The first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. This allows for the Stop bit transition to be at the correct sampling location (13 bits for Break versus Start bit and 8 data bits for typical data). The second method uses the auto-wake-up feature described in Section 15.2.4 "Auto-wake-up on Sync Break Character". By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Rate Detect feature. For both methods, the user can set the ABDEN bit once the TXIF interrupt is observed.
15.2.5.1
Break and Sync Transmit Sequence
The following sequence will send a message frame header made up of a Break, followed by an Auto-Baud Sync byte. This sequence is typical of a LIN/J2602 bus master. 1. 2. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to set up the Break character.
FIGURE 15-10:
Write to TXREG BRG Output (Shift Clock) TX (pin)
SEND BREAK CHARACTER SEQUENCE
Dummy Write
Start bit
bit 0
bit 1 Break
bit 11
Stop bit
TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) SENDB (Transmit Shift Reg. Empty Flag) SENDB Sampled Here Auto-Cleared
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15.3 EUSART Synchronous Master Mode
Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG is empty and the TXIF flag bit (PIR1<4>) is set. The interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, TXIE (PIE1<4>). TXIF is set regardless of the state of enable bit, TXIE; it cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read-only bit which is set when the TSR is empty. No interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory so it is not available to the user. To set up a Synchronous Master Transmission: 1. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. If interrupts are desired, set enable bit, TXIE. If 9-bit transmission is desired, set bit, TX9. Enable the transmission by setting bit, TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
The Master mode indicates that the processor transmits the master clock on the CK line. The Synchronous Master mode is entered by setting the CSRC bit (TXSTA<7>). In this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit, SPEN (RCSTA<7>), is set in order to configure the TX and RX pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. Clock polarity is selected with the SCKP bit (BAUDCON<4>). Setting SCKP sets the Idle state on CK as high, while clearing the bit sets the Idle state as low.
15.3.1
EUSART SYNCHRONOUS MASTER TRANSMISSION
2. 3. 4. 5. 6. 7. 8.
The EUSART transmitter block diagram is shown in Figure 15-3. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The Shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available).
FIGURE 15-11:
SYNCHRONOUS TRANSMISSION
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 7 bit 0 bit 1
bit 7
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RA3/RX/DT RA2/TX/CK pin ( = 0) Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit TXEN bit `1' Write Word 1
bit 0
bit 1
bit 2
Word 1
Word 2
Write Word 2
`1'
Note:
Sync Master mode, SPBRG = 0, continuous transmission of two 8-bit words.
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PIC18F1230/1330
FIGURE 15-12: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit 0 bit 1 bit 2 bit 6 bit 7 RA3/RX/DT pin
RA2/TX/CK pin Write to TXREG reg
TXIF bit
TRMT bit
TXEN bit
TABLE 15-7:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA BAUDCON SPBRGH SPBRG
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC TXCKP Bit 3 RBIE CMP2IF CMP2IE CMP2IP ADDEN SENDB BRG16 Bit 2 TMR0IF CMP1IF CMP1IE CMP1IP FERR BRGH -- Bit 1 INT0IF CMP0IF CMP0IE CMP0IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on Page: 47 49 49 49 48 48 48 48 48 48
GIE/GIEH PEIE/GIEL TMR0IE -- -- -- SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL RCIF RCIE RCIP SREN TXEN RXDTP
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission.
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15.3.2 EUSART SYNCHRONOUS MASTER RECEPTION
Once Synchronous mode is selected, reception is enabled by setting either the Single Receive Enable bit, SREN (RCSTA<5>), or the Continuous Receive Enable bit, CREN (RCSTA<4>). Data is sampled on the RX pin on the falling edge of the clock. If enable bit, SREN, is set, only a single word is received. If enable bit, CREN, is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. To set up a Synchronous Master Reception: 1. 2. 3. If any error occurred, clear the error by clearing bit, CREN. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. Initialize the SPBRGH:SPBRG registers for the appropriate baud rate. Set or clear the BRG16 bit, as required, to achieve the desired baud rate. Enable the synchronous master serial port by setting bits, SYNC, SPEN and CSRC. 5. Ensure bits, CREN and SREN, are clear. 6. If the signal from the CK pin is to be inverted, set the TXCKP bit. 7. If interrupts are desired, set enable bit, RCIE. 8. If 9-bit reception is desired, set bit, RX9. 9. If a single reception is required, set bit, SREN. For continuous reception, set bit, CREN. 10. Interrupt flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if the enable bit, RCIE, was set. 11. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 12. Read the 8-bit received data by reading the RCREG register. 4.
FIGURE 15-13:
RA3/RX/DT pin RA2/TX/CK pin (TXCKP) Write to bit SREN SREN bit CREN bit `0' RCIF bit (Interrupt) Read RXREG
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
`0'
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 15-8:
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRGH SPBRG
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN RXDTP Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC TXCKP Bit 3 RBIE CMP2IF CMP2IE CMP2IP ADDEN SENDB BRG16 Bit 2 TMR0IF CMP1IF CMP1IE CMP1IP FERR BRGH -- Bit 1 INT0IF CMP0IF CMP0IE CMP0IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on Page: 47 49 49 49 48 48 48 48 48 48
GIE/GIEH PEIE/GIEL -- -- -- SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIDL
EUSART Receive Register
BAUDCON ABDOVF
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception.
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15.4 EUSART Synchronous Slave Mode
To set up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC. Clear bits, CREN and SREN. If interrupts are desired, set enable bit, TXIE. If the signal from the CK pin is to be inverted, set the TXCKP bit. If 9-bit transmission is desired, set bit, TX9. Enable the transmission by setting enable bit, TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit, TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set.
Synchronous Slave mode is entered by clearing bit, CSRC (TXSTA<7>). This mode differs from the Synchronous Master mode in that the shift clock is supplied externally at the CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in any low-power mode.
2. 3. 4. 5. 6. 7. 8. 9.
15.4.1
EUSART SYNCHRONOUS SLAVE TRANSMISSION
The operation of the Synchronous Master and Slave modes are identical, except in the case of the Sleep mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in the TXREG register. Flag bit, TXIF, will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit, TXIF, will now be set. If enable bit, TXIE, is set, the interrupt will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector.
e)
TABLE 15-9:
Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA BAUDCON SPBRGH SPBRG
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC TXCKP Bit 3 RBIE CMP2IF CMP2IE CMP2IP ADDEN SENDB BRG16 Bit 2 TMR0IF CMP1IF CMP1IE CMP1IP FERR BRGH -- Bit 1 INT0IF CMP0IF CMP0IE CMP0IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on Page: 47 49 49 49 48 48 48 48 48 48
GIE/GIEH PEIE/GIEL TMR0IE -- -- -- SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL RCIF RCIE RCIP SREN TXEN RXDTP
EUSART Transmit Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission.
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15.4.2 EUSART SYNCHRONOUS SLAVE RECEPTION
To set up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits, SYNC and SPEN, and clearing bit, CSRC. 2. If interrupts are desired, set enable bit, RCIE. 3. If the signal from the CK pin is to be inverted, set the TXCKP bit. 4. If 9-bit reception is desired, set bit, RX9. 5. To enable reception, set enable bit, CREN. 6. Flag bit, RCIF, will be set when reception is complete. An interrupt will be generated if enable bit, RCIE, was set. 7. Read the RCSTA register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing bit, CREN. 10. If using interrupts, ensure that the GIE and PEIE bits in the INTCON register (INTCON<7:6>) are set. The operation of the Synchronous Master and Slave modes is identical, except in the case of Sleep, or any Idle mode and bit SREN, which is a "don't care" in Slave mode. If receive is enabled by setting the CREN bit prior to entering Sleep or any Idle mode, then a word may be received while in this low-power mode. Once the word is received, the RSR register will transfer the data to the RCREG register; if the RCIE enable bit is set, the interrupt generated will wake the chip from the lowpower mode. If the global interrupt is enabled, the program will branch to the interrupt vector.
TABLE 15-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA BAUDCON SPBRGH SPBRG Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC TXCKP Bit 3 RBIE CMP2IF CMP2IE CMP2IP ADDEN SENDB BRG16 Bit 2 TMR0IF CMP1IF CMP1IE CMP1IP FERR BRGH -- Bit 1 INT0IF CMP0IF CMP0IE CMP0IP OERR TRMT WUE Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D ABDEN Reset Values on Page: 47 49 49 49 48 48 48 48 48 48
GIE/GIEH PEIE/GIEL TMR0IE -- -- -- SPEN CSRC ABDOVF ADIF ADIE ADIP RX9 TX9 RCIDL RCIF RCIE RCIP SREN TXEN RXDTP
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte EUSART Baud Rate Generator Register Low Byte
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception.
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16.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The ADCON0 register, shown in Register 16-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 16-2, configures the functions of the port pins. The ADCON2 register, shown in Register 16-3, configures the A/D clock source, programmed acquisition time and justification.
The Analog-to-Digital (A/D) Converter module has 4 inputs for the 18/20/28-pin devices. This module allows conversion of an analog input signal to a corresponding 10-bit digital number in PIC18F1230/ 1330 devices. The module has five registers: * * * * * A/D Result Register High Byte (ADRESH) A/D Result Register Low Byte (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2)
REGISTER 16-1:
R/W-0 SEVTEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7
ADCON0: A/D CONTROL REGISTER 0
U-0 -- U-0 -- U-0 -- R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SEVTEN: Special Event Trigger Enable bit 1 = Special Event Trigger from Power Control PWM module is enabled 0 = Special Event Trigger from Power Control PWM module is disabled (default) Unimplemented: Read as `0' CHS1:CHS0: Analog Channel Select bits 00 = Channel 0 (AN0) 01 = Channel 1 (AN1) 10 = Channel 2 (AN2) 11 = Channel 3 (AN3) GO/DONE: A/D Conversion Status bit When ADON = 1: 1 = A/D conversion in progress 0 = A/D Idle ADON: A/D On bit 1 = A/D Converter module is enabled 0 = A/D Converter module is disabled
bit 6-4 bit 3-2
bit 1
bit 0
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REGISTER 16-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCON1: A/D CONTROL REGISTER 1
U-0 -- U-0 -- R/W-0 VCFG0 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0
Unimplemented: Read as `0' VCFG0: Voltage Reference Configuration bit (VREF+ source) 1 = Positive reference for the A/D is VREF+ 0 = Positive reference for the A/D is AVDD PCFG3: A/D Port Configuration bit for RA6/AN3 0 = Port is configured as AN3 1 = Port is configured as RA6 PCFG2: A/D Port Configuration bit for RA4/AN2 0 = Port is configured as AN2 1 = Port is configured as RA4 PCFG1: A/D Port Configuration bit for RA1/AN1 0 = Port is configured as AN1 1 = Port is configured as RA1 PCFG0: A/D Port Configuration bit for RA0/AN0 0 = Port is configured as AN0 1 = Port is configured as RA0
bit 3
bit 2
bit 1
bit 0
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REGISTER 16-3:
R/W-0 ADFM bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCON2: A/D CONTROL REGISTER 2
U-0 -- R/W-0 ACQT2 R/W-0 ACQT1 R/W-0 ACQT0 R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 bit 0
ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified Unimplemented: Read as `0' ACQT2:ACQT0: A/D Acquisition Time Select bits 111 = 20 TAD 110 = 16 TAD 101 = 12 TAD 100 = 8 TAD 011 = 6 TAD 010 = 4 TAD 001 = 2 TAD 000 = 0 TAD(1) ADCS2:ADCS0: A/D Conversion Clock Select bits 111 = FRC (clock derived from A/D RC oscillator)(1) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock derived from A/D RC oscillator)(1) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 If the A/D FRC clock source is selected, a delay of one TCY (instruction cycle) is added before the A/D clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
bit 6 bit 5-3
bit 2-0
Note 1:
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The analog reference voltage is software selectable to the device's positive supply voltage (VDD), or the voltage level on the RA4/T0CKI/AN2/VREF+ pin. The A/D Converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D Converter's internal RC oscillator. The output of the sample and hold is the input into the A/D Converter, which generates the result via successive approximation. A device Reset forces all registers to their Reset state. This forces the A/D module to be turned off and any conversion in progress is aborted. Each port pin associated with the A/D Converter can be configured as an analog input or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH:ADRESL register pair, the GO/DONE bit (ADCON0 register) is cleared and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 16-1.
FIGURE 16-1:
A/D BLOCK DIAGRAM
CHS1:CHS0
10-Bit A/D Converter
VAIN (Input Voltage)
0011 0010
AN3 AN2 AN1 AN0
VCFG0 AVDD Reference Voltage VREF+ 0 1
0001 0000
AVSS
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The value in the ADRESH:ADRESL registers is not modified for a Power-on Reset. The ADRESH:ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine acquisition time, see Section 16.2 "A/D Acquisition Requirements". After this acquisition time has elapsed, the A/D conversion can be started. An acquisition time can be programmed to occur between setting the GO/DONE bit and the actual start of the conversion. The following steps should be followed to perform an A/ D conversion:
Digital Code Output
5.
Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts.
6. 7.
FIGURE 16-2:
3FFh 3FEh
A/D TRANSFER FUNCTION
1.
2.
3. 4.
Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D acquisition time (ADCON2) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time (if required). Start conversion: * Set GO/DONE bit (ADCON0 register)
003h 002h 001h 000h
3 LSB
1022.5 LSB
Analog Input Voltage
FIGURE 16-3:
ANALOG INPUT MODEL
VDD VT = 0.6V RIC 1k Sampling Switch SS RSS
Rs
ANx
VAIN
CPIN 5 pF VT = 0.6V
ILEAKAGE 100 nA
CHOLD = 25 pF
VSS
Legend: CPIN = Input Capacitance VT = Threshold Voltage ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch SS = Sample/Hold Capacitance (from DAC) CHOLD RSS = Sampling Switch Resistance
VDD
6V 5V 4V 3V 2V 1 2 3 4
Sampling Switch (k)
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1023.5 LSB
1 LSB
0.5 LSB
1.5 LSB
2 LSB
2.5 LSB
1022 LSB
1023 LSB
PIC18F1230/1330
16.1 Triggering A/D Conversions
The A/D conversion can be triggered by setting the GO/ DONE bit. This bit can either be set manually by the programmer or by setting the SEVTEN bit of ADCON0. When the SEVTEN bit is set, the Special Event Trigger from the Power Control PWM module triggers the A/D conversion. For more information, see Section 14.14 "PWM Special Event Trigger". selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. Note: When the conversion is started, the holding capacitor is disconnected from the input pin.
16.2
A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 16-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5 k. After the analog input channel is
To calculate the minimum acquisition time, Equation 16-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Example 16-3 shows the calculation of the minimum required acquisition time, TACQ. This calculation is based on the following application system assumptions: CHOLD Rs Conversion Error VDD Temperature = = = = 25 pF 2.5 k 1/2 LSb 5V RSS = 2 k 85C (system max.)
EQUATION 16-1:
TACQ = =
ACQUISITION TIME
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TAMP + TC + TCOFF
EQUATION 16-2:
VHOLD or TC = =
A/D MINIMUM CHARGING TIME
(VREF - (VREF/2048)) * (1 - e(-TC/CHOLD(RIC + RSS + RS))) -(CHOLD)(RIC + RSS + RS) ln(1/2048)
EQUATION 16-3:
TACQ TAMP TCOFF = = = 0.2 s
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
TAMP + TC + TCOFF (Temp - 25C)(0.02 s/C) (85C - 25C)(0.02 s/C) 1.2 s -(CHOLD)(RIC + RSS + RS) ln(1/2047) -(25 pF) (1 k + 2 k + 2.5 k) ln(0.0004883) 1.05 s 0.2 s + 1 s + 1.2 s 2.4 s
Temperature coefficient is only required for temperatures > 25C. Below 25C, TCOFF = 0 ms. TC =
TACQ
=
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16.3 Selecting and Configuring Acquisition Time 16.4 Selecting the A/D Conversion Clock
The ADCON2 register allows the user to select an acquisition time that occurs each time the GO/DONE bit is set. It also gives users the option to use an automatically determined acquisition time. Acquisition time may be set with the ACQT2:ACQT0 bits (ADCON2<5:3>), which provide a range of 2 to 20 TAD. When the GO/DONE bit is set, the A/D module continues to sample the input for the selected acquisition time, then automatically begins a conversion. Since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the GO/DONE bit. Manual acquisition is selected when ACQT2:ACQT0 = 000. When the GO/DONE bit is set, sampling is stopped and a conversion begins. The user is responsible for ensuring the required acquisition time has passed between selecting the desired input channel and setting the GO/DONE bit. This option is also the default Reset state of the ACQT2:ACQT0 bits and is compatible with devices that do not offer programmable acquisition times. In either case, when the conversion is completed, the GO/DONE bit is cleared, the ADIF flag is set and the A/D begins sampling the currently selected channel again. If an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 11 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal RC Oscillator
For correct A/D conversions, the A/D conversion clock (TAD) must be as short as possible, but greater than the minimum TAD (see parameter 130 for more information). Table 16-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 16-1:
TAD vs. DEVICE OPERATING FREQUENCIES
AD Clock Source (TAD) Maximum Device Frequency PIC18F1230/1330 2.86 MHz 5.71 MHz 11.43 MHz 22.86 MHz 40.0 MHz 40.0 MHz 1.00 MHz(1) PIC18LF1230/1330(4) 1.43 MHz 2.86 MHz 5.72 MHz 11.43 MHz 22.86 MHz 22.86 MHz 1.00 MHz(2)
Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC(3) Note 1: 2: 3: 4:
ADCS2:ADCS0 000 100 001 101 010 110 x11
The RC source has a typical TAD time of 1.2 s. The RC source has a typical TAD time of 2.5 s. For device frequencies above 1 MHz, the device must be in Sleep for the entire conversion or the A/D accuracy may be out of specification. Low-power (PIC18LF1230/1330) devices only.
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16.5 Operation in Power-Managed Modes 16.6 Configuring Analog Port Pins
The selection of the automatic acquisition time and A/D conversion clock is determined in part by the clock source and frequency while in a power-managed mode. If the A/D is expected to operate while the device is in a power-managed mode, the ACQT2:ACQT0 and ADCS2:ADCS0 bits in ADCON2 should be updated in accordance with the clock source to be used in that mode. After entering the mode, an A/D acquisition or conversion may be started. Once started, the device should continue to be clocked by the same clock source until the conversion has been completed. If desired, the device may be placed into the corresponding Idle mode during the conversion. If the device clock frequency is less than 1 MHz, the A/D RC clock source should be selected. Operation in Sleep mode requires the A/D FRC clock to be selected. If bits ACQT2:ACQT0 are set to `000' and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the SLEEP instruction and entry to Sleep mode. The IDLEN bit (OSCCON<7>) must have already been cleared prior to starting the conversion. The ADCON1 and TRISA registers configure the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS1:CHS0 bits and the TRIS bits. Note 1: When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert as analog inputs. Analog levels on a digitally configured input will be accurately converted. 2: Analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device's specification limits.
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16.7 A/D Conversions
Figure 16-4 shows the operation of the A/D Converter after the GO/DONE bit has been set and the ACQT2:ACQT0 bits are cleared. A conversion is started after the following instruction to allow entry into Sleep mode before the conversion begins. Figure 16-5 shows the operation of the A/D Converter after the GO/DONE bit has been set, the ACQT2:ACQT0 bits are set to `010' and a 4 TAD acquisition time is selected before the conversion starts. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample. This means that the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is completed or aborted, a 2 TAD wait is required before the next acquisition can be started. After this wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
16.8
Discharge
The discharge phase is used to initialize the value of the capacitor array. The array is discharged before every sample. This feature helps to optimize the unitygain amplifier, as the circuit always needs to charge the capacitor array, rather than charge/discharge based on previous measure values.
FIGURE 16-4:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)
TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 TAD1 b4 b1 b0 b6 b7 b2 b9 b8 b3 b5 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. Discharge
FIGURE 16-5:
A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)
TACQT Cycles 1 2 3 4 1 2 b9 3 b8 4 b7
TAD Cycles 5 b6 6 b5 7 b4 8 b3 9 b2 10 b1 11 b0 Discharge TAD1
Automatic Acquisition Time
Conversion starts (Holding capacitor is disconnected)
Set GO/DONE bit (Holding capacitor continues acquiring input)
On the following cycle: ADRESH:ADRESL are loaded, GO/DONE bit is cleared, ADIF bit is set, holding capacitor is connected to analog input.
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TABLE 16-2:
Name INTCON PIR1 PIE1 IPR1 ADRESH ADRESL ADCON0 ADCON1 ADCON2 PORTA TRISA
REGISTERS ASSOCIATED WITH A/D OPERATION
Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE CMP2IF CMP2IE CMP2IP Bit 2 TMR0IF CMP1IF CMP1IE CMP1IP Bit 1 INT0IF CMP0IF CMP0IE CMP0IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Reset Values on Page: 47 49 49 49 48 48 -- VCFG0 ACQT1 RA4 CHS1 PCFG3 ACQT0 RA3 CHS0 PCFG2 ADCS2 RA2 GO/DONE PCFG1 ADCS1 RA1 ADON PCFG0 ADCS0 RA0 48 48 48 50 49
GIE/GIEH PEIE/GIEL -- -- -- ADIF ADIE ADIP
A/D Result Register High Byte A/D Result Register Low Byte SEVTEN -- ADFM RA7(1) -- -- -- RA6(1) -- -- ACQT2 RA5(2)
TRISA7(1) TRISA6(1) PORTA Data Direction Control Register
Legend: -- = unimplemented, read as `0'. Shaded cells are not used for A/D conversion. Note 1: PORTA<7:6> and their direction bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 2: The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as `0'. This bit is read-only.
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17.0 COMPARATOR MODULE
The analog comparator module contains three comparators. The inputs can be selected from the analog inputs multiplexed with pins RA0, RB2 and RB3, as well as the on-chip voltage reference (see Section 18.0 "Comparator Voltage Reference Module"). The digital outputs are not available at the pin level and can only be read through the control register, CMCON (Register 17-1). CMCON also selects the comparator input.
REGISTER 17-1:
R-0 C2OUT bit 7 Legend: R = Readable bit -n = Value at POR bit 7
CMCON: COMPARATOR CONTROL REGISTER
R-0 R-0 C0OUT U-0 -- U-0 -- R/W-0 CMEN2 R/W-0 CMEN1 R/W-0 CMEN0 bit 0
C1OUT
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
C2OUT: Comparator 2 Output bit 1 = C2 VIN+ > C2 VIN- (CVREF) 0 = C2 VIN+ < C2 VIN- (CVREF) C1OUT: Comparator 1 Output bit 1 = C1 VIN+ > C1 VIN- (CVREF) 0 = C1 VIN+ < C1 VIN- (CVREF)C0OUT: Comparator 0 Output bit 1 = C0 VIN+ > C0 VIN- (CVREF) 0 = C0 VIN+ < C0 VIN- (CVREF) Unimplemented: Read as `0' CMEN2: Comparator 2 Enable bit 1 = Comparator 2 is enabled 0 = Comparator 2 is disabled CMEN1: Comparator 1 Enable bit 1 = Comparator 1 is enabled 0 = Comparator 1 is disabled CMEN0: Comparator 0 Enable bit 1 = Comparator 0 is enabled 0 = Comparator 0 is disabled
bit 6
bit 5
bit 4-3 bit 2
bit 1
bit 0
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17.1 Comparator Configuration 17.5 Comparator Outputs
For every analog comparator, there is a control bit called CMENx in the CMCON register. By setting the CMENx bit, the corresponding comparator can be enabled. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 23.0 "Electrical Characteristics". Note: Comparator interrupts should be disabled during a Comparator mode change; otherwise, a false interrupt may occur. The comparator outputs are read through the CxOUT bits of the CMCON register. These bits are read-only. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Note 1: When reading the PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input according to the Schmitt Trigger input specification. 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified.
17.2
Comparator Operation
A single comparator is shown in Figure 17-1, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ (CMPx) is less than the analog input VIN- (CVREF), the output of the comparator is a digital low level. When the analog input at VIN+ (CMPx) is greater than the analog input VIN- (CVREF), the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 17-1 represent the uncertainty due to input offsets and response time.
17.6
Comparator Interrupts
17.3
Comparator Reference
In this comparator module, an internal voltage reference is used (see Section 18.0 "Comparator Voltage Reference Module").
The comparator interrupt flag is set whenever there is a change in the output value of the corresponding comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:5>, to determine the actual change that occurred. The CMPxIF bit (PIR1<3:1>) is the Comparator Interrupt Flag. The CMPxIF bit must be reset by clearing it. Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. Both the CMPxIE bit (PIE1<3:1>) and the PEIE bit (INTCON<6>) must be set to enable the interrupt for the corresponding comparator. In addition, the GIE bit (INTCON<7>) must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMPxIF bit will still be set if an interrupt condition occurs. Note: If a change in the CMCON register (C2OUT, C1OUT or C0OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMPxIF (PIR1 register) interrupt flag may not get set.
FIGURE 17-1:
VIN+ VIN-
SINGLE COMPARATOR
+ -
Output
VINVIN+
The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) c) Any read or write of CMCON will end the mismatch condition. Clear flag bit CMPxIF. Input returning to original state.
Output
17.4
Comparator Response Time
A mismatch condition will continue to set flag bit CMPxIF. Reading CMCON will end the mismatch condition and allow flag bit CMPxIF to be cleared.
Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (see Section 23.0 "Electrical Characteristics").
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17.7 Comparator Operation During Sleep 17.9 Analog Input Connection Considerations
When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode when enabled. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in Sleep mode, turn off the comparators (CMEN2:CMEN0 = 000) before entering Sleep. If the device wakes up from Sleep, the contents of the CMCON register are not affected.
17.8
Effects of a Reset
A simplified circuit for an analog input is shown in Figure 17-2. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or Zener diode, should have very little leakage current.
A device Reset forces the CMCON register to its Reset state, causing the comparator modules to be turned off (CMEN2:CMEN0 = 000).
FIGURE 17-2:
COMPARATOR ANALOG INPUT MODEL
VDD RS < 10k AIN VT = 0.6V RIC Comparator Input CPIN 5 pF VT = 0.6V ILEAKAGE 100 nA
VA
VSS Legend: CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage
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TABLE 17-1:
Name CMCON CVRCON INTCON PIR1 PIE1 IPR1 PORTA LATA TRISA PORTB LATB TRISB
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Bit 7 C2OUT CVREN -- -- -- RA7(1) LATA7
(1)
Bit 6 C1OUT -- ADIF ADIE ADIP RA6(1) LATA6(1) RB6
Bit 5 C0OUT CVRR TMR0IE RCIF RCIE RCIP RA5(2)
Bit 4 -- CVRSS INT0IE TXIF TXIE TXIP RA4
Bit 3 -- CVR3 RBIE CMP2IF CMP2IE CMP2IP RA3
Bit 2 CMEN2 CVR2 TMR0IF CMP1IF CMP1IE CMP1IP RA2
Bit 1 CMEN1 CVR1 INT0IF CMP0IF CMP0IE CMP0IP RA1
Bit 0 CMEN0 CVR0 RBIF TMR1IF TMR1IE TMR1IP RA0
Reset Values on Page: 48 48 47 49 49 49 50 49 49
GIE/GIEH PEIE/GIEL
PORTA Data Latch Register (Read and Write to Data Latch) RB5 RB4 RB3 RB2 RB1 RB0
TRISA7(1) RB7
TRISA6(1) PORTA Data Direction Control Register
50 49 49
PORTB Data Latch Register (Read and Write to Data Latch) PORTB Data Direction Control Register
Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the comparator module. Note 1: PORTA<7:6> and their direction and latch bits are individually configured as port pins based on various primary oscillator modes. When disabled, these bits read as `0'. 2: The RA5 bit is only available when Master Clear Reset is disabled (MCLRE Configuration bit = 0); otherwise, RA5 reads as `0'. This bit is read-only.
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18.0 COMPARATOR VOLTAGE REFERENCE MODULE
The comparator reference supply voltage can come from either AVDD or AVSS, or the external VREF+ that is multiplexed with RA4 and AVSS. The voltage source is selected by the CVRSS bit (CVRCON<4>). Additionally, the voltage reference can select the unscaled VREF+ input for use by the comparators, bypassing the CVREF module. (See Table 18-1 and Figure 18-1.) The settling time of the comparator voltage reference must be considered when changing the CVREF output (see Table 23-3 in Section 23.0 "Electrical Characteristics").
The comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. Its purpose is to provide a reference for the analog comparators. A block diagram of the module is shown in Figure 18-1. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The module's supply reference can be provided from either device VDD/VSS or an external voltage reference.
TABLE 18-1:
CVREN 0 0 1 1 CVRSS 0 1 0 1
18.1
Configuring the Comparator Voltage Reference
VOLTAGE REFERENCE OUTPUT
CVREF Disabled Disabled Enabled Enabled Comparator Input No reference From VREF (CVREF bypassed) From CVREF From CVREF
The voltage reference module is controlled through the CVRCON register (Register 18-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF selection bits (CVR3:CVR0), with one range offering finer resolution. The equations used to calculate the output of the comparator voltage reference are as follows: If CVRR = 1: CVREF = ((CVR3:CVR0)/24) x CVRSRC If CVRR = 0: CVREF = (CVRSRC x 1/4) + (((CVR3:CVR0)/32) x CVRSRC)
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REGISTER 18-1:
R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 -- R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 R/W-0 CVR0 bit 0
CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down Unimplemented: Read as `0' CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.667 CVRSRC, with CVRSRC/24 step size (low range) 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size (high range) CVRSS: Comparator VREF Source Selection bit When CVRR = 1 1 = Comparator reference source, CVRSRC = (VREF+) - (AVSS) 0 = Comparator reference source, CVRSRC = AVDD - AVSS When CVRR = 0 1 = VREF+ input used directly, comparator voltage reference bypassed 0 = No reference is provided CVR3:CVR0: Comparator VREF Value Selection bits (0 (CVR3:CVR0) 15) When CVRR = 1: CVREF = ((CVR3:CVR0)/24) (CVRSRC) When CVRR = 0: CVREF = (CVRSRC/4) + ((CVR3:CVR0)/32) (CVRSRC)
bit 6 bit 5
bit 4
bit 3-0
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FIGURE 18-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
VREF+ AVDD
CVRSS = 0
8R R R R
CVR3:CVR0
CVREN
16-to-1 MUX
R 16 Steps
CVREN = 0 CVREN = 1 CVREF
R R R CVRR
8R
AVSS
CVRSS = x
18.2
Voltage Reference Accuracy/Error
18.3
Operation During Sleep
The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 18-1) keep CVREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the CVREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 23.0 "Electrical Characteristics".
When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the CVRCON register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled.
18.4
Effects of a Reset
A device Reset disables the voltage reference by clearing bit, CVREN (CVRCON<7>). This Reset selects the highvoltage range by clearing bit, CVRR (CVRCON<5>). The CVR value select bits are also cleared.
TABLE 18-2:
Name CVRCON CMCON
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 7 CVREN C2OUT Bit 6 -- C1OUT Bit 5 CVRR C0OUT Bit 4 CVRSS -- Bit 3 CVR3 -- Bit 2 CVR2 CMEN2 Bit 1 CVR1 CMEN1 Bit 0 CVR0 CMEN0 Reset Values on Page: 48 48
Legend: Shaded cells are not used with the comparator voltage reference.
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NOTES:
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19.0 LOW-VOLTAGE DETECT (LVD)
PIC18F1230/1330 devices have a Low-Voltage Detect module (LVD). This is a programmable circuit that allows the user to specify the device voltage trip point. If the device experiences an excursion past the trip point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. The Low-Voltage Detect Control register (Register 19-1) completely controls the operation of the LVD module. This allows the circuitry to be "turned off" by the user under software control, which minimizes the current consumption for the device. The block diagram for the LVD module is shown in Figure 19-1.
REGISTER 19-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5
LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER
U-0 -- R-0 IRVST R/W-0 LVDEN R/W-0 LVDL3(1) R/W-1 LVDL2(1) R/W-0 LVDL1(1) R/W-1 LVDL0(1) bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the voltage detect logic will generate the interrupt flag at the specified voltage trip point 0 = Indicates that the voltage detect logic will not generate the interrupt flag at the specified voltage trip point and the LVD interrupt should not be enabled LVDEN: Low-Voltage Detect Power Enable bit 1 = LVD enabled 0 = LVD disabled LVDL3:LVDL0: Voltage Detection Limit bits(1) 1111 = Reserved 1110 = Maximum setting . . . 0000 = Minimum setting See Table 23-4 in Section 23.0 "Electrical Characteristics" for the specifications.
bit 4
bit 3-0
Note 1:
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The module is enabled by setting the LVDEN bit. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit is a read-only bit and is used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. trip point voltage. The "trip point" voltage is the voltage level at which the device detects a low-voltage event depending on the configuration of the module. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array is equal to the internal reference voltage generated by the voltage reference module. The comparator then generates an interrupt signal by setting the LVDIF bit. The trip point voltage is software programmable to any 1 of 15 values. The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>).
19.1
Operation
When the LVD module is enabled, a comparator uses an internally generated reference voltage as the set point. The set point is compared with the trip point, where each node in the resistor divider represents a
FIGURE 19-1:
LVD MODULE BLOCK DIAGRAM
VDD
LVDL3:LVDL0
LVDCON Register LVDEN
16-to-1 MUX
Set LVDIF
LVDEN
BORENx
Internal Voltage Reference
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19.2 LVD Setup
The following steps are needed to set up the LVD module: 1. 2. 3. 4. 5. Disable the module by clearing the LVDEN bit (LVDCON<4>). Write the value to the LVDL3:LVDL0 bits that selects the desired LVD trip point. Enable the LVD module by setting the LVDEN bit. Clear the LVD interrupt flag (PIR2<2>) which may have been set from a previous interrupt. Enable the LVD interrupt, if interrupts are desired, by setting the LVDIE and GIE bits (PIE2<2> and INTCON<7>). An interrupt will not be generated until the IRVST bit is set. Depending on the application, the LVD module does not need to be operating constantly. To decrease the current requirements, the LVD circuitry may only need to be enabled for short periods where the voltage is checked. After doing the check, the LVD module may be disabled.
19.4
LVD Start-up Time
19.3
Current Consumption
When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static current. The total current consumption, when enabled, is specified in electrical specification parameter D022B.
The internal reference voltage of the LVD module, specified in electrical specification parameter D420, may be used by other internal circuitry, such as the programmable Brown-out Reset. If the LVD or other circuits using the voltage reference are disabled to lower the device's current consumption, the reference voltage circuit will require time to become stable before a low-voltage condition can be reliably detected. This start-up time, TIRVST, is an interval that is independent of device clock speed. It is specified in electrical specification parameter 36. The LVD interrupt flag is not enabled until TIRVST has expired and a stable reference voltage is reached. For this reason, brief excursions beyond the set point may not be detected during this interval (refer to Figure 19-2).
FIGURE 19-2:
CASE 1:
LOW-VOLTAGE DETECT OPERATION
LVDIF may not be set VDD VLVD
LVDIF Enable LVD IRVST TIRVST Internal reference is stable CASE 2: VDD VLVD LVDIF Enable LVD IRVST Internal reference is stable LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists TIRVST LVDIF cleared in software
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19.5 Applications 19.6 Operation During Sleep
In many applications, the ability to detect a drop below a particular threshold is desirable. For general battery applications, Figure 19-3 shows a possible voltage curve. Over time, the device voltage decreases. When the device voltage reaches voltage VA, the LVD logic generates an interrupt at time TA. The interrupt could cause the execution of an ISR, which would allow the application to perform "housekeeping tasks" and perform a controlled shutdown before the device voltage exits the valid operating range at TB. The LVD, thus, would give the application a time window, represented by the difference between TA and TB, to safely exit. When enabled, the LVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wakeup from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled.
19.7
Effects of a Reset
A device Reset forces all registers to their Reset state. This forces the LVD module to be turned off.
FIGURE 19-3:
TYPICAL LOW-VOLTAGE DETECT APPLICATION
VA VB Voltage
Time
TA
TB
Legend: VA = LVD trip point VB = Minimum valid device operating voltage
TABLE 19-1:
Name LVDCON INTCON PIR2 PIE2 IPR2
REGISTERS ASSOCIATED WITH LOW-VOLTAGE DETECT MODULE
Bit 7 -- OSCFIF OSCFIE OSCFIP Bit 6 -- -- -- -- Bit 5 IRVST TMR0IE -- -- -- Bit 4 LVDEN INT0IE EEIF EEIE EEIP Bit 3 LVDL3 RBIE -- -- -- Bit 2 LVDL2 TMR0IF LVDIF LVDIE LVDIP Bit 1 LVDL1 INT0IF -- -- -- Bit 0 LVDL0 RBIF -- -- -- Reset Values on Page: 48 47 49 49 49
GIE/GIEH PEIE/GIEL
Legend: -- = unimplemented, read as `0'. Shaded cells are unused by the LVD module.
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20.0 SPECIAL FEATURES OF THE CPU
The inclusion of an internal RC oscillator also provides the additional benefits of a Fail-Safe Clock Monitor (FSCM) and Two-Speed Start-up. FSCM provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. TwoSpeed Start-up enables code to be executed almost immediately on start-up while the primary clock source completes its start-up delays. All of these features are enabled and configured by setting the appropriate Configuration register bits.
PIC18F1230/1330 devices include several features intended to maximize reliability and minimize cost through elimination of external components. These are: * Oscillator Selection * Resets: - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Fail-Safe Clock Monitor * Two-Speed Start-up * Code Protection * ID Locations * In-Circuit Serial Programming The oscillator can be configured for the application depending on frequency, power, accuracy and cost. All of the options are discussed in detail in Section 3.0 "Oscillator Configurations". A complete discussion of device Resets and interrupts is available in previous sections of this data sheet. In addition to their Power-up and Oscillator Start-up Timers provided for Resets, PIC18F1230/1330 devices have a Watchdog Timer, which is either permanently enabled via the Configuration bits or software controlled (if configured as disabled).
20.1
Configuration Bits
The Configuration bits can be programmed (read as `0') or left unprogrammed (read as `1') to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh) which can only be accessed using table reads and table writes. Programming the Configuration registers is done in a manner similar to programming the Flash memory. The WR bit in the EECON1 register starts a self-timed write to the Configuration register. In normal operation mode, a TBLWT instruction with the TBLPTR pointing to the Configuration register sets up the address and data for the Configuration register write. Setting the WR bit starts a long write to the Configuration register. The Configuration registers are written a byte at a time. To write or erase a configuration cell, a TBLWT instruction can write a `1' or a `0' into the cell. For additional details on Flash programming, refer to Section 7.5 "Writing to Flash Program Memory".
TABLE 20-1:
File Name 300001h 300002h 300003h 300004h 300005h 300006h 300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh 3FFFFEh 3FFFFFh Legend: Note 1:
CONFIGURATION BITS AND DEVICE IDs
Bit 7 IESO -- -- -- Bit 6 FCMEN -- -- -- -- XINST -- CPB -- WRTB -- EBTRB DEV1 DEV9 Bit 5 -- -- -- -- -- BBSIZ1 -- -- -- WRTC -- -- DEV0 DEV8 Bit 4 -- BORV1 WDTPS3 -- -- BBSIZ0 -- -- -- -- -- -- REV4 DEV7 Bit 3 FOSC3 BORV0 WDTPS2 HPOL T1OSCMX -- -- -- -- -- -- -- REV3 DEEV6 Bit 2 FOSC2 Bit 1 FOSC1 Bit 0 FOSC0 Default/ Unprogrammed Value 00-- 0111 ---1 1111 ---1 1111 ---- 1111--- 0--1 1000 ---1 ---- --11 11-- ------- --11 111- ------- --11 -1-- ---See Table 20-2 See Table 20-2
CONFIG1H CONFIG2L CONFIG2H CONFIG3L
BOREN1 BOREN0 PWRTEN WDTPS1 WDTPS0 WDTEN LPOL -- -- -- -- -- -- -- -- REV2 DEV5 PWMPIN -- -- CP1 -- WRT1 -- EBTR1 -- REV1 DEV4 -- FLTAMX STVREN CP0 -- WRT0 -- EBTR0 -- REV0 DEV3
CONFIG3H MCLRE CONFIG4L BKBUG CONFIG5L CONFIG5H CONFIG6L CONFIG7L CONFIG7H DEVID1(1) DEVID2
(1)
-- CPD -- -- -- DEV2 DEV10
CONFIG6H WRTD
- = unimplemented, read as `0'.Shaded cells are unimplemented, read as `0'. DEVID registers are read-only and cannot be programmed by the user.
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REGISTER 20-1:
R/P-0 IESO bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7
CONFIG1H: CONFIGURATION REGISTER 1 HIGH (BYTE ADDRESS 300001h)
R/P-0 U-0 -- U-0 -- R/P-0 FOSC3 R/P-1 FOSC2 R/P-1 FOSC1 R/P-1 FOSC0 bit 0
FCMEN
IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled Unimplemented: Read as `0' FOSC3:FOSC0: Oscillator Selection bits 11xx = External RC oscillator, CLKO function on RA6 101x = External RC oscillator, CLKO function on RA6 1001 = Internal oscillator block, CLKO function on RA6, port function on RA7 1000 = Internal oscillator block, port function on RA6 and RA7 0111 = External RC oscillator, port function on RA6 0110 = HS oscillator, PLL enabled (Clock Frequency = 4 x FOSC1) 0101 = EC oscillator, port function on RA6 0100 = EC oscillator, CLKO function on RA6 0011 = External RC oscillator, CLKO function on RA6 0010 = HS oscillator 0001 = XT oscillator 0000 = LP oscillator
bit 6
bit 5-4 bit 3-0
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REGISTER 20-2:
U-0 -- bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-5 bit 4-3 Unimplemented: Read as `0' BORV1:BORV0: Brown-out Reset Voltage bits(1) 11 = Minimum setting * * * 00 = Maximum setting BOREN1:BOREN0: Brown-out Reset Enable bits(2) 11 = Brown-out Reset enabled in hardware only (SBOREN is disabled) 10 = Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled) 01 = Brown-out Reset enabled and controlled by software (SBOREN is enabled) 00 = Brown-out Reset disabled in hardware and software PWRTEN: Power-up Timer Enable bit(2) 1 = PWRT disabled 0 = PWRT enabled See Section 23.1 "DC Characteristics" for the specifications. The Power-up Timer is decoupled from Brown-out Reset, allowing these features to be independently controlled.
CONFIG2L: CONFIGURATION REGISTER 2 LOW (BYTE ADDRESS 300002h)
U-0 -- U-0 -- R/P-1 BORV1
(1)
R/P-1 BORV0
(1)
R/P-1 BOREN1
(2)
R/P-1 BOREN0
(2)
R/P-1 PWRTEN(2) bit 0
bit 2-1
bit 0
Note 1: 2:
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REGISTER 20-3:
U-0 -- bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-5 bit 4-1 Unimplemented: Read as `0' WDTPS3:WDTPS0: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit)
CONFIG2H: CONFIGURATION REGISTER 2 HIGH (BYTE ADDRESS 300003h)
U-0 -- U-0 -- R/P-1 WDTPS3 R/P-1 WDTPS2 R/P-1 WDTPS1 R/P-1 WDTPS0 R/P-1 WDTEN bit 0
bit 0
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REGISTER 20-4:
U-0 -- bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-4 bit 3 Unimplemented: Read as `0' HPOL: High Side Transistors Polarity bit (Odd PWM Output Polarity Control bit)(1) 1 = PWM1, PWM3 and PWM5 are active-high (default) 0 = PWM1, PWM3 and PWM5 are active-low LPOL: Low Side Transistors Polarity bit (Even PWM Output Polarity Control bit)(1) 1 = PWM0, PWM2 and PWM4 are active-high (default) 0 = PWM0, PWM2 and PWM4 are active-low PWMPIN: PWM Output Pins Reset State Control bit 1 = PWM outputs disabled upon Reset 0 = PWM outputs drive active states upon Reset(2) Unimplemented: Read as `0' Polarity control bits, HPOL and LPOL, define PWM signal output active and inactive states, PWM states generated by the Fault inputs or PWM manual override. When PWMPIN = 0, PWMEN<2:0> = 100. PWM output polarity is defined by HPOL and LPOL.
CONFIG3L: CONFIGURATION REGISTER 3 LOW (BYTE ADDRESS 300005h)
U-0 -- U-0 -- U-0 -- R/P-1 HPOL
(1)
R/P-1 LPOL
(1)
R/P-1 PWMPIN
U-0 -- bit 0
bit 2
bit 2
bit 0 Note 1: 2:
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REGISTER 20-5:
R/P-1 MCLRE bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7
CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
U-0 -- U-0 -- U-0 -- R/P-0 T1OSCMX U-0 -- U-0 -- R/P-1 FLTAMX bit 0
MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled, RA5 input pin disabled 0 = RA5 input pin enabled, MCLR pin disabled Unimplemented: Read as `0' T1OSCMX: T1OSO/T1CKI MUX bit 1 = T1OSO/T1CKI pin resides on RA6 0 = T1OSO/T1CKI pin resides on RB2 Unimplemented: Read as `0' FLTAMX: FLTA MUX bit 1 = FLTA is muxed onto RA5 0 = FLTA is muxed onto RA7
bit 6-4 bit 3
bit 2-1 bit 0
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REGISTER 20-6:
R/P-1 BKBUG bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7
CONFIG4L: CONFIGURATION REGISTER 4 LOW (BYTE ADDRESS 300006h)
R/P-0 XINST R/P-0 BBSIZ1 R/P-0 BBSIZ0 U-0 -- U-0 -- U-0 -- R/P-1 STVREN bit 0
BKBUG: Background Debugger Enable bit 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug XINST: Extended Instruction Set Enable bit 1 = Instruction set extension and Indexed Addressing mode enabled 0 = Instruction set extension and Indexed Addressing mode disabled BBSIZ<1:0>: Boot Block Size Select bits For PIC18F1330 device: 11 = 1 kW Boot Block size 10 = 1 kW Boot Block size 01 = 512W Boot Block size 00 = 256W Boot Block size For PIC18F1230 device: 11 = 512W Boot Block size 10 = 512W Boot Block size 01 = 512W Boot Block size 00 = 256W Boot Block size Unimplemented: Maintain as `0' Unimplemented: Read as `0' STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Reset on stack overflow/underflow enabled 0 = Reset on stack overflow/underflow disabled
bit 6
bit 5-4
bit 3 bit 2-1 bit 0
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REGISTER 20-7:
U-0 -- bit 7 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-2 bit 1 Unimplemented: Read as `0' CP1: Code Protection bit (Block 1 Code Memory Area) 1 = Block 1 is not code-protected 0 = Block 1 is code-protected CP0: Code Protection bit (Block 0 Code Memory Area) 1 = Block 0 is not code-protected 0 = Block 0 is code-protected
CONFIG5L: CONFIGURATION REGISTER 5 LOW (BYTE ADDRESS 300008h)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/C-1 CP1 R/C-1 CP0 bit 0
bit 0
REGISTER 20-8:
R/C-1 CPD bit 7 Legend: R = Readable bit
CONFIG5H: CONFIGURATION REGISTER 5 HIGH (BYTE ADDRESS 300009h)
R/C-1 CPB U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
C = Clearable bit
U = Unimplemented bit, read as `0' u = Unchanged from programmed state
-n = Value when device is unprogrammed bit 7 CPD: Code Protection bit (Data EEPROM) 1 = Data EEPROM is not code-protected 0 = Data EEPROM is code-protected
bit 6
CPB: Code Protection bit (Boot Block Memory Area) 1 = Boot Block is not code-protected 0 = Boot Block is code-protected Unimplemented: Read as `0'
bit 5-0
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REGISTER 20-9:
U-0 -- bit 7 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-2 bit 1 Unimplemented: Read as `0' WRT1: Write Protection bit (Block 1 Code Memory Area) 1 = Block 1 is not write-protected 0 = Block 1 is write-protected WRT0: Write Protection bit (Block 0 Code Memory Area) 1 = Block 0 is not write-protected 0 = Block 0 is write-protected
CONFIG6L: CONFIGURATION REGISTER 6 LOW (BYTE ADDRESS 30000Ah)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/C-1 WRT1 R/C-1 WRT0 bit 0
bit 0
REGISTER 20-10: CONFIG6H: CONFIGURATION REGISTER 6 HIGH (BYTE ADDRESS 30000Bh)
R/C-1 WRTD bit 7 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7 R/C-1 WRTB R-1 WRTC(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
WRTD: Write Protection bit (Data EEPROM) 1 = Data EEPROM is not write-protected 0 = Data EEPROM is write-protected WRTB: Write Protection bit (Boot Block Memory Area) 1 = Boot Block is not write-protected 0 = Boot Block is write-protected WRTC: Write Protection bit (Configuration Registers)(1) 1 = Configuration registers are not write-protected 0 = Configuration registers are write-protected Unimplemented: Read as `0' This bit is read-only in normal execution mode; it can be written only in Program mode.
bit 6
bit 5
bit 4-0 Note 1:
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REGISTER 20-11: CONFIG7L: CONFIGURATION REGISTER 7 LOW (BYTE ADDRESS 30000Ch)
U-0 -- bit 7 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-2 bit 1 Unimplemented: Read as `0' EBTR1: Table Read Protection bit (Block 1 Code Memory Area) 1 = Block 1 is not protected from table reads executed in other blocks 0 = Block 1 is protected from table reads executed in other blocks EBTR0: Table Read Protection bit (Block 0 Code Memory Area) 1 = Block 0 is not protected from table reads executed in other blocks 0 = Block 0 is protected from table reads executed in other blocks It is recommended to enable the corresponding CPx bit to protect block from external read operations. U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/C-1 EBTR1(1) R/C-1 EBTR0(1) bit 0
bit 0
Note 1:
REGISTER 20-12: CONFIG7H: CONFIGURATION REGISTER 7 HIGH (BYTE ADDRESS 30000Dh)
U-0 -- bit 7 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7 bit 6 Unimplemented: Read as `0' EBTRB: Table Read Protection bit (Boot Block Memory Area) 1 = Boot Block is not protected from table reads executed in other blocks 0 = Boot Block is protected from table reads executed in other blocks Unimplemented: Read as `0' It is recommended to enable the corresponding CPx bit to protect block from external read operations. R/C-1 EBTRB(1) U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 5-0 Note 1:
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REGISTER 20-13: DEVID1: DEVICE ID REGISTER 1 FOR PIC18F1230/1330 DEVICES
R DEV2 bit 7 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-5 DEV2:DEV0: Device ID bits 000 = PIC18F1230 001 = PIC18F1330 REV3:REV0: Revision ID bits These bits are used to indicate the device revision. R DEV1 R DEV0 R REV4 R REV3 R REV2 R REV1 R REV0 bit 0
bit 4-0
REGISTER 20-14: DEVID2: DEVICE ID REGISTER 2 FOR PIC18F1230/1330 DEVICES
R DEV10 bit 7 Legend: R = Read-only bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state -n = Value when device is unprogrammed bit 7-0 R DEV9 R DEV8 R DEV7 R DEV6 R DEV5 R DEV4 R DEV3 bit 0
DEV10:DEV3: Device ID bits(1) 0001 1110 = PIC18F1230/1330 devices These bits are used with the DEV2:DEV0 bits in the DEVID1 register to identify part number. Note 1: The values for DEV10:DEV3 may be shared with other devices. A device can be identified by using the entire DEV10:DEV0 bit sequence.
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20.2 Watchdog Timer (WDT)
For PIC18F1230/1330 devices, the WDT is driven by the INTRC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the INTRC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes). The WDT and postscaler are cleared when any of the following events occur: a SLEEP or CLRWDT instruction is executed, the IRCF bits (OSCCON<6:4>) are changed or a clock failure has occurred. Note 1: The CLRWDT and SLEEP instructions clear the WDT and postscaler counts when executed. 2: Changing the setting of the IRCF bits (OSCCON<6:4>) clears the WDT and postscaler counts. 3: When a CLRWDT instruction is executed, the postscaler count will be cleared.
20.2.1
CONTROL REGISTER
Register 20-15 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable Configuration bit, but only if the Configuration bit has disabled the WDT.
FIGURE 20-1:
WDT BLOCK DIAGRAM
Enable WDT WDT Counter
SWDTEN WDTEN INTRC Source Change on IRCF bits CLRWDT All Device Resets WDTPS<3:0> Sleep
128
Wake-up from Power-Managed Modes Programmable Postscaler 1:1 to 1:32,768 4 Reset WDT Reset
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REGISTER 20-15: WDTCON: WATCHDOG TIMER CONTROL REGISTER
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SWDTEN(1) bit 0
Unimplemented: Read as `0' SWDTEN: Software Controlled Watchdog Timer Enable bit(1) 1 = Watchdog Timer is on 0 = Watchdog Timer is off This bit has no effect if the Configuration bit, WDTEN, is enabled.
Note 1:
TABLE 20-2:
Name RCON WDTCON
SUMMARY OF WATCHDOG TIMER REGISTERS
Bit 7 IPEN -- Bit 6 SBOREN(1) -- Bit 5 -- -- Bit 4 RI -- Bit 3 TO -- Bit 2 PD -- Bit 1 POR -- Bit 0 BOR SWDTEN(2) Reset Values on Page: 48 48
Legend: -- = unimplemented, read as `0'. Shaded cells are not used by the Watchdog Timer. Note 1: The SBOREN bit is only available when the BOREN1:BOREN0 Configuration bits = 01; otherwise, it is disabled and reads as `0'. See Section 5.4 "Brown-out Reset (BOR)". 2: This bit has no effect if the Configuration bit, WDTEN, is enabled.
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20.3 Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the latency period from oscillator start-up to code execution by allowing the microcontroller to use the INTOSC oscillator as a clock source until the primary clock source is available. It is enabled by setting the IESO Configuration bit. Two-Speed Start-up should be enabled only if the primary oscillator mode is LP, XT, HS or HSPLL (crystal-based modes). Other sources do not require an OST start-up delay; for these, Two-Speed Start-up should be disabled. When enabled, Resets and wake-ups from Sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the Power-up Timer, after a Power-on Reset is enabled. This allows almost immediate code execution while the primary oscillator starts and the OST is running. Once the OST times out, the device automatically switches to PRI_RUN mode. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IRCF2:IRCF0, immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF2:IRCF0 bits prior to entering Sleep mode. In all other power-managed modes, Two-Speed Start-up is not used. The device will be clocked by the currently selected clock source until the primary clock source becomes available. The setting of the IESO bit is ignored.
20.3.1
SPECIAL CONSIDERATIONS FOR USING TWO-SPEED START-UP
While using the INTOSC oscillator in Two-Speed Start-up, the device still obeys the normal command sequences for entering power-managed modes, including multiple SLEEP instructions (refer to Section 4.1.4 "Multiple Sleep Commands"). In practice, this means that user code can change the SCS1:SCS0 bit settings or issue SLEEP instructions before the OST times out. This would allow an application to briefly wake-up, perform routine "housekeeping" tasks and return to Sleep before the device starts to operate from the primary oscillator. User code can also check if the primary clock source is currently providing the device clocking by checking the status of the OSTS bit (OSCCON<3>). If the bit is set, the primary oscillator is providing the clock. Otherwise, the internal oscillator block is providing the clock during wake-up from Reset or Sleep mode.
FIGURE 20-2:
INTOSC Multiplexer OSC1
TIMING TRANSITION FOR TWO-SPEED START-UP (INTOSC TO HSPLL)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
TOST(1) PLL Clock Output CPU Clock Peripheral Clock Program Counter PC
TPLL(1) 1 2 n-1 n
Clock Transition(2)
PC + 2 OSTS bit Set
PC + 4
PC + 6
Wake from Interrupt Event
Note 1: 2:
TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. Clock transition typically occurs within 2-4 TOSC.
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20.4 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. The FSCM function is enabled by setting the FCMEN Configuration bit. When FSCM is enabled, the INTRC oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure. Clock monitoring (shown in Figure 20-3) is accomplished by creating a sample clock signal, which is the INTRC output divided by 64. This allows ample time between FSCM sample clocks for a peripheral clock edge to occur. The peripheral device clock and the sample clock are presented as inputs to the Clock Monitor latch (CM). The CM is set on the falling edge of the device clock source, but cleared on the rising edge of the sample clock. To use a higher clock speed on wake-up, the INTOSC or postscaler clock sources can be selected to provide a higher clock speed by setting bits, IRCF2:IRCF0, immediately after Reset. For wake-ups from Sleep, the INTOSC or postscaler clock sources can be selected by setting the IRCF2:IRCF0 bits prior to entering Sleep mode. The FSCM will detect failures of the primary or secondary clock sources only. If the internal oscillator block fails, no failure would be detected, nor would any action be possible.
20.4.1
FSCM AND THE WATCHDOG TIMER
Both the FSCM and the WDT are clocked by the INTRC oscillator. Since the WDT operates with a separate divider and counter, disabling the WDT has no effect on the operation of the INTRC oscillator when the FSCM is enabled. As already noted, the clock source is switched to the INTOSC clock when a clock failure is detected. Depending on the frequency selected by the IRCF2:IRCF0 bits, this may mean a substantial change in the speed of code execution. If the WDT is enabled with a small prescale value, a decrease in clock speed allows a WDT time-out to occur and a subsequent device Reset. For this reason, fail-safe clock events also reset the WDT and postscaler, allowing it to start timing from when execution speed was changed and decreasing the likelihood of an erroneous time-out.
FIGURE 20-3:
FSCM BLOCK DIAGRAM
Clock Monitor Latch (CM) (edge-triggered) S Q
Peripheral Clock
INTRC Source (32 s)
/ 64 488 Hz (2.048 ms)
C
Q
20.4.2
Clock Failure Detected
EXITING FAIL-SAFE OPERATION
Clock failure is tested for on the falling edge of the sample clock. If a sample clock falling edge occurs while CM is still set, a clock failure has been detected (Figure 20-4). This causes the following: * The FSCM generates an oscillator fail interrupt by setting bit, OSCFIF (PIR2<7>). * The device clock source is switched to the internal oscillator block (OSCCON is not updated to show the current clock source - this is the fail-safe condition). * The WDT is reset. During switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. In these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. This can be done to attempt a partial recovery or execute a controlled shutdown. See Section 4.1.4 "Multiple Sleep Commands" and Section 20.3.1 "Special Considerations for Using Two-Speed Start-up" for more details.
The fail-safe condition is terminated by either a device Reset or by entering a power-managed mode. On Reset, the controller starts the primary clock source specified in Configuration Register 1H (with any required start-up delays that are required for the oscillator mode, such as the OST or PLL timer). The INTOSC multiplexer provides the device clock until the primary clock source becomes ready (similar to a TwoSpeed Start-up). The clock source is then switched to the primary clock (indicated by the OSTS bit in the OSCCON register becoming set). The Fail-Safe Clock Monitor then resumes monitoring the peripheral clock. The primary clock source may never become ready during start-up. In this case, operation is clocked by the INTOSC multiplexer. The OSCCON register will remain in its Reset state until a power-managed mode is entered.
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FIGURE 20-4:
Sample Clock Device Clock Output CM Output (Q) OSCFIF Oscillator Failure
FSCM TIMING DIAGRAM
Failure Detected
CM Test Note:
CM Test
CM Test
The device clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
20.4.3
FSCM INTERRUPTS IN POWER-MANAGED MODES
By entering a power-managed mode, the clock multiplexer selects the clock source selected by the OSCCON register. Fail-Safe Clock Monitoring of the powermanaged clock source resumes in the power-managed mode. If an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. If enabled (OSCFIF = 1), code execution will be clocked by the INTOSC multiplexer. An automatic transition back to the failed clock source will not occur. If the interrupt is disabled, subsequent interrupts while in Idle mode will cause the CPU to begin executing instructions while being clocked by the INTOSC source.
time considerably longer than the FCSM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the device clock and functions until the primary clock is stable (the OST and PLL timers have timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source. Note: The same logic that prevents false oscillator failure interrupts on POR, or wake from Sleep, will also prevent the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged.
20.4.4
POR OR WAKE FROM SLEEP
The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or low-power Sleep mode. When the primary device clock is EC, RC or INTRC modes, monitoring can begin immediately following these events. For oscillator modes involving a crystal or resonator (HS, HSPLL, LP or XT), the situation is somewhat different. Since the oscillator may require a start-up
As noted in Section 20.3.1 "Special Considerations for Using Two-Speed Start-up", it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. When the new powermanaged mode is selected, the primary clock is disabled.
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20.5 Program Verification and Code Protection
Each of the three blocks has three code protection bits associated with them. They are: * Code-Protect bit (CPx) * Write-Protect bit (WRTx) * External Block Table Read bit (EBTRx) Figure 20-5 shows the program memory organization for 4 and 8-Kbyte devices and the specific code protection bit associated with each block. The actual locations of the bits are summarized in Table 20-3.
The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC(R) devices. The user program memory is divided into three blocks. One of these is a Boot Block of variable size (maximum 2 Kbytes). The remainder of the memory is divided into two blocks on binary boundaries.
FIGURE 20-5:
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F1230/1330
MEMORY SIZE/DEVICE
4 Kbytes (PIC18F1230) Boot Block
8 Kbytes (PIC18F1330)
Address Range 000000h 0003FFh
Block Code Protection Controlled By:
CPB, WRTB, EBTRB CP0, WRT0, EBTR0
Boot Block Block 0
000400h 0007FFh 000800h
Block 1
Block 0 000FFFh 001000h
CP1, WRT1, EBTR1
Unimplemented Read `0's
Block 1 001FFFh 002000h
CP2, WRT2, EBTR2
Unimplemented Read `0's
Unimplemented Read `0's
(Unimplemented Memory Space)
1FFFFFh
TABLE 20-3:
File Name 300008h 300009h 30000Ah 30000Bh 30000Ch 30000Dh
SUMMARY OF CODE PROTECTION REGISTERS
Bit 7 -- CPD -- WRTD -- -- Bit 6 -- CPB -- WRTB -- EBTRB Bit 5 -- -- -- WRTC -- -- Bit 4 -- -- -- -- -- -- Bit 3 -- -- -- -- -- -- Bit 2 -- -- -- -- -- -- Bit 1 CP1 -- WRT1 -- EBTR1 -- Bit 0 CP0 -- WRT0 -- EBTR0 --
CONFIG5L CONFIG5H CONFIG6L CONFIG6H CONFIG7L CONFIG7H
Legend: Shaded cells are unimplemented.
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20.5.1 PROGRAM MEMORY CODE PROTECTION
The program memory may be read to or written from any location using the table read and table write instructions. The Device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. In normal execution mode, the CPx bits have no direct effect. CPx bits inhibit external reads and writes. A block of user memory may be protected from table writes if the WRTx Configuration bit is `0'. The EBTRx bits control table reads. For a block of user memory with the EBTRx bit set to `0', a table read instruction that executes from within that block is allowed to read. A table read instruction that executes from a location outside of that block is not allowed to read and will result in reading `0's. Figures 20-6 through 20-8 illustrate table write and table read protection. Note: Code protection bits may only be written to a `0' from a `1' state. It is not possible to write a `1' to a bit in the `0' state. Code protection bits are only set to `1' by a full chip erase or block erase function. The full chip erase and block erase functions can only be initiated via ICSP operation or an external programmer.
FIGURE 20-6:
TABLE WRITE (WRTx) DISALLOWED
Program Memory 000000h 0007FFh 000800h WRTB, EBTRB = 11 Configuration Bit Settings
Register Values
TBLPTR = 0008FFh PC = 000FFEh 000FFFh 001000h
WRT0, EBTR0 = 01 TBLWT*
PC = 001800h
TBLWT*
WRT1, EBTR1 = 11
001FFFh Results: All table writes disabled to Blockn whenever WRTx = 0.
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FIGURE 20-7: EXTERNAL BLOCK TABLE READ (EBTRx) DISALLOWED
Program Memory 000000h 0007FFh 000800h TBLPTR = 0008FFh WRTB, EBTRB = 11 Configuration Bit Settings Register Values
WRT0, EBTR0 = 10 000FFFh 001000h WRT1, EBTR1 = 11
PC = 001100h
TBLRD*
001FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRx = 0. TABLAT register returns a value of `0'.
FIGURE 20-8:
EXTERNAL BLOCK TABLE READ (EBTRx) ALLOWED
Program Memory 000000h 0007FFh 000800h Configuration Bit Settings WRTB, EBTRB = 11
Register Values
TBLPTR = 0008FFh PC = 000FFEh TBLRD* 000FFFh 001000h
WRT0, EBTR0 = 10
WRT1, EBTR1 = 11
001FFFh Results: Table reads permitted within Blockn, even when EBTRBx = 0. TABLAT register returns the value of the data at the location TBLPTR.
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20.5.2 DATA EEPROM CODE PROTECTION
20.8
In-Circuit Debugger
The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings.
When the BKBUG Configuration bit is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) IDE. When the microcontroller has this feature enabled, some resources are not available for general use. Table 20-4 shows which resources are required by the background debugger.
20.5.3
CONFIGURATION REGISTER PROTECTION
TABLE 20-4:
I/O pins: Stack:
DEBUGGER RESOURCES
RB6, RB7 2 levels 512 bytes 10 bytes
The Configuration registers can be write-protected. The WRTC bit controls protection of the Configuration registers. In normal execution mode, the WRTC bit is read-only. WRTC can only be written via ICSP operation or an external programmer.
Program Memory: Data Memory:
20.6
ID Locations
Eight memory locations (200000h-200007h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are both readable and writable during normal execution through the TBLRD and TBLWT instructions or during program/verify. The ID locations can be read when the device is code-protected.
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP/RA5/FLTA, VDD, VSS, RB7/PWM5/PGD and RB6/PWM4/PGC. This will interface to the In-Circuit Debugger module available from Microchip or one of the third party development tool companies.
20.9
Single-Supply ICSP Programming
20.7
In-Circuit Serial Programming
PIC18F1230/1330 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
The PIC18F1230/1330 device family does not support Low-Voltage ICSP Programming or LVP. This device family can only be programmed using high-voltage ICSP programming. For more details, refer to the "PIC18F1230/1330 Flash Microcontroller Programming Specification" (DS39752). Memory that is not code-protected can be erased using either a block erase, or erased row by row, then written at any specified VDD. If code-protected memory is to be erased, a block erase is required.
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21.0 DEVELOPMENT SUPPORT
21.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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21.2 MPASM Assembler 21.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
21.6 21.3 MPLAB C18 and MPLAB C30 C Compilers
MPLAB SIM Software Simulator
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
21.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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21.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 21.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
21.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
21.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC(R) and MCU devices. It debugs and programs PIC(R) and dsPIC(R) Flash microcontrollers with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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21.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
21.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits.
21.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
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22.0 INSTRUCTION SET SUMMARY
PIC18F1230/1330 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by `k') * The desired FSR register to load the literal value into (specified by `f') * No operand required (specified by `--') The control instructions may use some of the following operands: * A program memory address (specified by `n') * The mode of the CALL or RETURN instructions (specified by `s') * The mode of the table read and table write instructions (specified by `m') * No operand required (specified by `--') All instructions are a single word, except for four double-word instructions. These instructions were made double-word to contain the required information in 32 bits. In the second word, the 4 MSbs are `1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. The double-word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two-word branch instructions (if true) would take 3 s. Figure 22-1 shows the general formats that the instructions can have. All examples use the convention `nnh' to represent a hexadecimal number. The Instruction Set Summary, shown in Table 22-2, lists the standard instructions recognized by the Microchip MPASMTM Assembler. Section 22.1.1 "Standard Instruction Set" provides a description of each instruction.
22.1
Standard Instruction Set
The standard PIC18 instruction set adds many enhancements to the previous PIC(R) MCU instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. Each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations
The PIC18 instruction set summary in Table 22-2 lists byte-oriented, bit-oriented, literal and control operations. Table 22-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The destination of the result (specified by `d') The accessed memory (specified by `a')
The file register designator `f' specifies which file register is to be used by the instruction. The destination designator `d' specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the WREG register. If `d' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by `f') The bit in the file register (specified by `b') The accessed memory (specified by `a')
The bit field designator `b' selects the number of the bit affected by the operation, while the file register designator `f' represents the number of the file in which the bit is located.
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TABLE 22-1:
Field a
OPCODE FIELD DESCRIPTIONS
Description RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register Bit address within an 8-bit file register (0 to 7). Bank Select Register. Used to select the current RAM bank. ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative. Destination select bit d = 0: store result in WREG d = 1: store result in file register f Destination: either the WREG register or the specified register file location. 8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h). 12-bit Register file address (000h to FFFh). This is the source address. 12-bit Register file address (000h to FFFh). This is the destination address. Global Interrupt Enable bit. Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). Label name. The mode of the TBLPTR register for the table read and table write instructions. Only used with table read and table write instructions: No change to register (such as TBLPTR with table reads and writes) Post-Increment register (such as TBLPTR with table reads and writes) Post-Decrement register (such as TBLPTR with table reads and writes) Pre-Increment register (such as TBLPTR with table reads and writes) The relative address (2's complement number) for relative branch instructions or the direct address for Call/Branch and Return instructions. Program Counter. Program Counter Low Byte. Program Counter High Byte. Program Counter High Byte Latch. Program Counter Upper Byte Latch. Power-Down bit. Product of Multiply High Byte. Product of Multiply Low Byte. Fast Call/Return mode select bit s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) 21-bit Table Pointer (points to a program memory location). 8-bit Table Latch. Time-out bit. Top-of-Stack. Unused or unchanged. Watchdog Timer. Working register (accumulator). Don't care (`0' or `1'). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. 7-bit offset value for indirect addressing of register files (source). 7-bit offset value for indirect addressing of register files (destination).
bbb BSR C, DC, Z, OV, N d
dest f fs fd GIE k label mm * *+ *+* n PC PCL PCH PCLATH PCLATU PD PRODH PRODL s
TBLPTR TABLAT TO TOS u WDT WREG x zs zd { } [text] (text) [expr] <> italics
Optional argument. Indicates an indexed address. The contents of text. Specifies bit n of the register indicated by the pointer expr. Assigned to. Register bit field. In the set of. User-defined term (font is Courier New).
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FIGURE 22-1: GENERAL FORMAT FOR INSTRUCTIONS
Byte-oriented file register operations 15 10 OPCODE d 9 87 a f (FILE #) 0 ADDWF MYREG, W, B Example Instruction
d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 15 1111 12 11 f (Source FILE #) 0 f (Destination FILE #) 12 11 0 MOVFF MYREG1, MYREG2 OPCODE
f = 12-bit file register address Bit-oriented file register operations 15 12 11 98 7 f (FILE #) 0 BSF MYREG, bit, B OPCODE b (BIT #) a
b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Literal operations 15 OPCODE k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 OPCODE 15 1111 12 11 n<19:8> (literal) 87 n<7:0> (literal) 0 0 GOTO Label 8 7 k (literal) 0 MOVLW 7Fh
n = 20-bit immediate value 15 OPCODE 15 1111 S = Fast bit 15 OPCODE 15 OPCODE 87 n<7:0> (literal) 11 10 n<10:0> (literal) 0 BC MYFUNC 0 BRA MYFUNC 12 11 n<19:8> (literal) 87 S n<7:0> (literal) 0 0 CALL MYFUNC
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TABLE 22-2:
Mnemonic, Operands
PIC18FXXXX INSTRUCTION SET
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB SUBWF SUBWFB SWAPF TSTFSZ XORWF Note 1: f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a Add WREG and f Add WREG and Carry bit to f AND WREG with f Clear f Complement f Compare f with WREG, Skip = Compare f with WREG, Skip > Compare f with WREG, Skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with Borrow Subtract WREG from f Subtract WREG from f with Borrow Swap Nibbles in f Test f, Skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 01da0 0010 00da 0001 01da 0110 101a 0001 11da 0110 001a 0110 010a 0110 000a 0000 01da 0010 11da 0100 11da 0010 10da 0011 11da 0100 10da 0001 00da 0101 00da 1100 ffff 1111 ffff 0110 111a 0000 001a 0110 110a 0011 01da 0100 01da 0011 00da 0100 00da 0110 100a 0101 01da 0101 0101 0011 0110 0001 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None None None C, DC, Z, OV, N C, Z, N Z, N C, Z, N Z, N None C, DC, Z, OV, N 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1
1, 2 1, 2
1, 2
ffff C, DC, Z, OV, N ffff C, DC, Z, OV, N ffff None ffff None ffff Z, N
1, 2
4 1, 2
2: 3: 4:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
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TABLE 22-2:
Mnemonic, Operands BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL CLRWDT DAW GOTO NOP NOP POP PUSH RCALL RESET RETFIE RETLW RETURN SLEEP Note 1: f, b, a f, b, a f, b, a f, b, a f, d, a n n n n n n n n n n, s -- -- n -- -- -- -- n s k s -- Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop Top of Return Stack (TOS) Push Top of Return Stack (TOS) Relative Call Software Device Reset Return from Interrupt Enable Return with Literal in WREG Return from Subroutine Go into Standby mode 1 1 1 (2 or 3) 1 (2 or 3) 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None None None None None None None None None None None TO, PD C None 1, 2 1, 2 3, 4 3, 4 1, 2
PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
CONTROL OPERATIONS 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s
None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD
4
2: 3: 4:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
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TABLE 22-2:
Mnemonic, Operands LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: k k k f, k k k k k k k Add Literal and WREG AND Literal with WREG Inclusive OR Literal with WREG Move Literal (12-bit) 2nd word to FSR(f) 1st word Move Literal to BSR<3:0> Move Literal to WREG Multiply Literal with WREG Return with Literal in WREG Subtract WREG from Literal Exclusive OR Literal with WREG Table Read Table Read with Post-Increment Table Read with Post-Decrement Table Read with Pre-Increment Table Write Table Write with Post-Increment Table Write with Post-Decrement Table Write with Pre-Increment 1 1 1 2 1 1 1 2 1 1 2 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z, OV, N Z, N Z, N None None None None None C, DC, Z, OV, N Z, N None None None None None None None None
PIC18FXXXX INSTRUCTION SET (CONTINUED)
16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
DATA MEMORY PROGRAM MEMORY OPERATIONS 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111
2
2: 3: 4:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and where applicable, `d' = 1), the prescaler will be cleared if assigned. If the Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
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22.1.1
ADDLW
Syntax: Operands: Operation: Status Affected: Encoding: Description:
STANDARD INSTRUCTION SET
ADD Literal to W
ADDLW 0 k 255 (W) + k W N, OV, C, DC, Z 0000 1111 kkkk kkkk The contents of W are added to the 8-bit literal `k' and the result is placed in W. 1 1 Q1 Q2 Read literal `k' Q3 Process Data Q4 Write to W Operation: Status Affected: Encoding: Description: k
ADDWF
Syntax: Operands:
ADD W to f
ADDWF 0 f 255 d [0,1] a [0,1] (W) + (f) dest N, OV, C, DC, Z 0010 01da ffff ffff Add W to register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 f {,d {,a}}
Words: Cycles: Q Cycle Activity: Decode
Example:
ADDLW
15h Words: Cycles:
Before Instruction W = 10h After Instruction W = 25h Q Cycle Activity: Q1 Decode
Q2 Read register `f'
Q3 Process Data
Q4 Write to destination
Example: W = REG = After Instruction W REG = =
ADDWF 17h 0C2h 0D9h 0C2h
REG, 0, 0
Before Instruction
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
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ADDWFC
Syntax: Operands:
ADD W and Carry bit to f
ADDWFC 0 f 255 d [0,1] a [0,1] (W) + (f) + (C) dest N,OV, C, DC, Z 0010 00da ffff ffff Add W, the Carry flag and data memory location `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 f {,d {,a}}
ANDLW
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
AND Literal with W
ANDLW 0 k 255 (W) .AND. k W N, Z 0000 1011 kkkk kkkk The contents of W are ANDed with the 8-bit literal `k'. The result is placed in W. 1 1 Q2 Read literal `k' ANDLW A3h 03h Q3 Process Data 05Fh Q4 Write to W k
Operation: Status Affected: Encoding: Description:
Example: W = After Instruction W =
Before Instruction
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' ADDWFC 1 02h 4Dh 0 02h 50h
Q3 Process Data REG, 0, 1
Q4 Write to destination
Example:
Before Instruction Carry bit = REG = W = After Instruction Carry bit = REG = W =
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ANDWF
Syntax: Operands:
AND W with f
ANDWF 0 f 255 d [0,1] a [0,1] (W) .AND. (f) dest N, Z 0001 01da ffff ffff The contents of W are ANDed with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Q2 Read register `f' ANDWF 17h C2h 02h C2h Q3 Process Data REG, 0, 0 Q4 Write to destination f {,d {,a}}
BC
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Carry
BC n -128 n 127 if Carry bit is `1', (PC) + 2 + 2n PC None 1110 0010 nnnn nnnn If the Carry bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BC 5
Q4 Write to PC No operation Q4 No operation
Words: Cycles: Q Cycle Activity: Decode
Example: W = REG = After Instruction W REG = =
Before Instruction
Example:
Before Instruction PC After Instruction If Carry PC If Carry PC
address (HERE) 1; address (HERE + 12) 0; address (HERE + 2)
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BCF
Syntax: Operands:
Bit Clear f
BCF f, b {,a} 0 f 255 0b7 a [0,1] 0 f None 1001 bbba ffff ffff Bit `b' in register `f' is cleared. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' BCF = = Q3 Process Data FLAG_REG, C7h 47h Q4 Write register `f' 7, 0
BN
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Negative
BN n -128 n 127 if Negative bit is `1', (PC) + 2 + 2n PC None 1110 0110 nnnn nnnn If the Negative bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1
Words: Cycles: Q Cycle Activity:
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BN Jump
Q4 Write to PC No operation Q4 No operation
Example:
Decode
Before Instruction FLAG_REG After Instruction FLAG_REG
Example:
Before Instruction PC After Instruction If Negative PC If Negative PC
address (HERE) 1; address (Jump) 0; address (HERE + 2)
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BNC
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Carry
BNC n -128 n 127 if Carry bit is `0', (PC) + 2 + 2n PC None 1110 0011 nnnn nnnn If the Carry bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
BNN
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Negative
BNN n -128 n 127 if Negative bit is `0', (PC) + 2 + 2n PC None 1110 0111 nnnn nnnn If the Negative bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Words: Cycles: Q Cycle Activity: If Jump: Q2 Q3 Process Data No operation Q3 Process Data BNC Jump Q4 Write to PC No operation Q4 No operation Q1 Decode No operation If No Jump: Q2 Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BNN Jump
Q4 Write to PC No operation Q4 No operation
Read literal `n' No operation
Read literal `n' HERE = = = = =
Example:
Example:
Before Instruction PC After Instruction If Carry PC If Carry PC
address (HERE) 0; address (Jump) 1; address (HERE + 2)
Before Instruction PC After Instruction If Negative PC If Negative PC
address (HERE) 0; address (Jump) 1; address (HERE + 2)
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BNOV
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Overflow
BNOV n -128 n 127 if Overflow bit is `0', (PC) + 2 + 2n PC None 1110 0101 nnnn nnnn If the Overflow bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
BNZ
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Not Zero
BNZ n -128 n 127 if Zero bit is `0', (PC) + 2 + 2n PC None 1110 0001 nnnn nnnn If the Zero bit is `0', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Words: Cycles: Q Cycle Activity: If Jump: Q2 Q3 Process Data No operation Q3 Process Data BNOV Jump address (HERE) 0; address (Jump) 1; address (HERE + 2) Q4 Write to PC No operation Q4 No operation Q1 Decode No operation If No Jump: Q2 Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BNZ Jump
Q4 Write to PC No operation Q4 No operation
Read literal `n' No operation
Read literal `n' HERE = = = = =
Example:
Example:
Before Instruction PC After Instruction If Overflow PC If Overflow PC
Before Instruction PC After Instruction If Zero PC If Zero PC
address (HERE) 0; address (Jump) 1; address (HERE + 2)
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BRA
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Unconditional Branch
BRA n -1024 n 1023 (PC) + 2 + 2n PC None 1101 0nnn nnnn nnnn Add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2 Q1 Decode No operation Q2 Read literal `n' No operation Q3 Process Data No operation Q4 Write to PC No operation
BSF
Syntax: Operands:
Bit Set f
BSF f, b {,a} 0 f 255 0b7 a [0,1] 1 f None 1000 bbba ffff ffff Bit `b' in register `f' is set. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' BSF = = Q3 Process Data Q4 Write register `f'
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity:
Words: Cycles: Q Cycle Activity:
Example:
HERE = =
BRA
Jump
Before Instruction PC After Instruction PC
address (HERE) address (Jump)
Example:
FLAG_REG, 7, 1 0Ah 8Ah
Before Instruction FLAG_REG After Instruction FLAG_REG
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BTFSC
Syntax: Operands:
Bit Test File, Skip if Clear
BTFSC f, b {,a} 0 f 255 0b7 a [0,1] skip if (f) = 0 None 1011 bbba ffff ffff If bit `b' in register `f' is `0', then the next instruction is skipped. If bit `b' is `0', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Decode Q2 Read register `f' Q2 No operation Q2 No operation No operation HERE FALSE TRUE = = = = = Q3 Process Data Q3 No operation Q3 No operation No operation BTFSC : : Q4 No operation
BTFSS
Syntax: Operands:
Bit Test File, Skip if Set
BTFSS f, b {,a} 0 f 255 0b<7 a [0,1] skip if (f) = 1 None 1010 bbba ffff ffff If bit `b' in register `f' is `1', then the next instruction is skipped. If bit `b' is `1', then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation BTFSS : : Q4 No operation Q4 No operation Q4 No operation No operation
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
Words: Cycles:
Words: Cycles:
Q Cycle Activity:
Q Cycle Activity: Q1 Decode If skip: Q2 Read register `f' Q2 No operation Q2 No operation No operation HERE FALSE TRUE = = = = =
If skip: Q1 No operation Q1 No operation No operation Example: Q4 No operation Q4 No operation No operation
Q1 No operation Q1 No operation No operation Example:
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
FLAG, 1, 0
FLAG, 1, 0
Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC
address (HERE) 0; address (TRUE) 1; address (FALSE)
Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC
address (HERE) 0; address (FALSE) 1; address (TRUE)
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BTG
Syntax: Operands:
Bit Toggle f
BTG f, b {,a} 0 f 255 0b<7 a [0,1] (f) f None 0111 bbba ffff ffff Bit `b' in data memory location `f' is inverted. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' BTG Q3 Process Data PORTC, 4, 0 Q4 Write register `f'
BOV
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Overflow
BOV n -128 n 127 if Overflow bit is `1', (PC) + 2 + 2n PC None 1110 0100 nnnn nnnn If the Overflow bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Words: Cycles: Q Cycle Activity:
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BOV Jump
Q4 Write to PC No operation Q4 No operation
Example:
Before Instruction: PORTC = 0111 0101 [75h] After Instruction: PORTC = 0110 0101 [65h]
Example:
Before Instruction PC After Instruction If Overflow PC If Overflow PC
address (HERE) 1; address (Jump) 0; address (HERE + 2)
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BZ
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Branch if Zero
BZ n -128 n 127 if Zero bit is `1', (PC) + 2 + 2n PC None 1110 0000 nnnn nnnn If the Zero bit is `1', then the program will branch. The 2's complement number `2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
CALL
Syntax: Operands: Operation:
Subroutine Call
CALL k {,s} 0 k 1048575 s [0,1] (PC) + 4 TOS, k PC<20:1>; if s = 1, (W) WS, (STATUS) STATUSS, (BSR) BSRS None 1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8
Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description:
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Q2 Read literal `n' No operation Q2 Read literal `n' HERE = = = = =
Q3 Process Data No operation Q3 Process Data BZ Jump
Q4 Write to PC No operation Q4 No operation Words: Cycles: Q Cycle Activity: Q1 Decode
Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If `s' = 1, the W, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If `s' = 0, no update occurs. Then, the 20-bit value `k' is loaded into PC<20:1>. CALL is a two-cycle instruction. 2 2 Q2 Q3 Q4 Read literal `k'<19:8>, Write to PC No operation
Read literal PUSH PC to `k'<7:0>, stack No operation HERE No operation CALL
Example:
Before Instruction PC After Instruction If Zero PC If Zero PC
address (HERE) 1; address (Jump) 0; address (HERE + 2)
No operation Example:
THERE, 1
Before Instruction PC = After Instruction PC = TOS = WS = BSRS = STATUSS =
address (HERE) address (THERE) address (HERE + 4) W BSR STATUS
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CLRF
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Clear f
CLRF f {,a} 0 f 255 a [0,1] 000h f, 1Z Z 0110 101a ffff ffff
CLRWDT
Syntax: Operands: Operation:
Clear Watchdog Timer
CLRWDT None 000h WDT, 000h WDT postscaler, 1 TO, 1 PD TO, PD 0000 0000 0000 0100
Status Affected: Encoding: Description:
Clears the contents of the specified register. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set.
1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 No operation CLRWDT = = = = = ?
Q3 Process Data
Q4 No operation
Words: Cycles: Q Cycle Activity: Q1 Decode
Example: Q2 Q3 Process Data FLAG_REG, 1 5Ah 00h Q4 Write register `f'
Read register `f' CLRF = =
Example:
Before Instruction WDT Counter After Instruction WDT Counter WDT Postscaler TO PD
00h 0 1 1
Before Instruction FLAG_REG After Instruction FLAG_REG
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COMF
Syntax: Operands:
Complement f
COMF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) dest N, Z 0001 11da ffff ffff The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
CPFSEQ
Syntax: Operands: Operation:
Compare f with W, Skip if f = W
CPFSEQ 0 f 255 a [0,1] (f) - (W), skip if (f) = (W) (unsigned comparison) None 0110 001a ffff ffff Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If `f' = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Q2 Read register `f' Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation f {,a}
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Q1 Decode
Words: Q2 Read register `f' COMF 13h If skip: 13h ECh Q3 Process Data REG, 0, 0 Q4 Write to destination Cycles:
Q Cycle Activity: Example: Before Instruction REG = After Instruction REG = W = Decode
Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NEQUAL EQUAL = = = = = =
CPFSEQ REG, 0 : : HERE ? ? W; Address (EQUAL) W; Address (NEQUAL)
Before Instruction PC Address W REG After Instruction If REG PC If REG PC
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CPFSGT
Syntax: Operands: Operation:
Compare f with W, Skip if f > W
CPFSGT 0 f 255 a [0,1] (f) -W), skip if (f) > (W) (unsigned comparison) None 0110 010a ffff ffff Compares the contents of data memory location `f' to the contents of the W by performing an unsigned subtraction. If the contents of `f' are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. f {,a}
CPFSLT
Syntax: Operands: Operation:
Compare f with W, Skip if f < W
CPFSLT 0 f 255 a [0,1] (f) -W), skip if (f) < (W) (unsigned comparison) None 0110 000a ffff ffff Compares the contents of data memory location `f' to the contents of W by performing an unsigned subtraction. If the contents of `f' are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation Q4 No operation Q4 No operation Q4 No operation No operation f {,a}
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 Q2 No operation Q2 No operation No operation HERE NLESS LESS = = < = = No operation Q1 Q2 Read register `f'
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NGREATER GREATER = = = = Q4 No operation Q4 No operation No operation Q2 Read register `f' Q3 Process Data Q4 No operation
If skip and followed by 2-word instruction: No operation No operation Example:
CPFSLT REG, 1 : : Address (HERE) ? W; Address (LESS) W; Address (NLESS)
CPFSGT REG, 0 : :
Before Instruction PC W After Instruction If REG PC If REG PC
Before Instruction PC W After Instruction If REG PC If REG PC
Address (HERE) ? W; Address (GREATER) W; Address (NGREATER)
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DAW
Syntax: Operands: Operation:
Decimal Adjust W Register
DAW None If [W<3:0> > 9] or [DC = 1] then, (W<3:0>) + 6 W<3:0>; else, (W<3:0>) W<3:0> If [W<7:4> + DC > 9] or [C = 1] then, (W<7:4>) + 6 + DC W<7:4>; else, (W<7:4>) + DC W<7:4>
DECF
Syntax: Operands:
Decrement f
DECF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) - 1 dest C, DC, N, OV, Z 0000 01da ffff ffff Decrement register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' DECF 01h 0 00h 1 Q3 Process Data CNT, 1, 0 Q4 Write to destination
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
C 0000 0000 0000 0111 DAW adjusts the eight-bit value in W resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. 1 1 Words: Q2 Read register W DAW Q3 Process Data Q4 Write W Cycles: Q Cycle Activity:
Words: Cycles: Q Cycle Activity: Q1 Decode Example 1:
Before Instruction W = C = DC = After Instruction W C DC Example 2: = = = A5h 0 0 05h 1 0
Example:
Before Instruction CNT = Z = After Instruction CNT = Z =
Before Instruction W = C = DC = After Instruction W C DC = = = CEh 0 0 34h 1 0
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DECFSZ
Syntax: Operands:
Decrement f, Skip if 0
DECFSZ f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result = 0 None 0010 11da ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Q2 Read register `f' Q2 No operation Q2 No operation No operation HERE CONTINUE Q3 Process Data Q3 No operation Q3 No operation No operation DECFSZ GOTO Q4 Write to destination Q4 No operation Q4 No operation No operation CNT, 1, 1 LOOP
DCFSNZ
Syntax: Operands:
Decrement f, Skip if Not 0
DCFSNZ 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result 0 None 0100 11da ffff ffff The contents of register `f' are decremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. If the result is not `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation DCFSNZ : : = = = = = ? TEMP - 1 0; Address (ZERO) 0; Address (NZERO) Q4 Write to destination Q4 No operation Q4 No operation No operation f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 Q2 Decode If skip: Q1 No operation Q1 No operation No operation Example:
Read register `f'
If skip and followed by 2-word instruction:
No operation Q2 No operation No operation HERE ZERO NZERO
If skip and followed by 2-word instruction:
TEMP, 1, 0
Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC =
Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2)
Before Instruction TEMP After Instruction TEMP If TEMP PC If TEMP PC
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GOTO
Syntax: Operands: Operation: Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description:
Unconditional Branch
GOTO k 0 k 1048575 k PC<20:1> None 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8
INCF
Syntax: Operands:
Increment f
INCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) + 1 dest C, DC, N, OV, Z 0010 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' INCF FFh 0 ? ? 00h 1 1 1 Q3 Process Data CNT, 1, 0 Q4 Write to destination
Operation: Status Affected: Encoding: Description:
GOTO allows an unconditional branch
anywhere within entire 2-Mbyte memory range. The 20-bit value `k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction.
Words: Cycles: Q Cycle Activity: Q1 Decode
2 2 Q2 Read literal `k'<7:0>, No operation GOTO THERE Q3 No operation No operation Q4 Read literal `k'<19:8>, Write to PC No operation
No operation Example:
Words: Cycles: Q Cycle Activity:
After Instruction PC = Address (THERE)
Example:
Before Instruction CNT = Z = C = DC = After Instruction CNT = Z = C = DC =
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INCFSZ
Syntax: Operands:
Increment f, Skip if 0
INCFSZ 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result = 0 None 0011 11da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. If the result is `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Q2 Read register `f' Q2 No operation Q2 No operation No operation HERE NZERO ZERO Q3 Process Data Q3 No operation Q3 No operation No operation INCFSZ : : Q4 Write to destination f {,d {,a}}
INFSNZ
Syntax: Operands:
Increment f, Skip if Not 0
INFSNZ 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result 0 None 0100 10da ffff ffff The contents of register `f' are incremented. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. If the result is not `0', the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation INFSNZ Q4 Write to destination Q4 No operation Q4 No operation No operation f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Decode If skip: Q1 No operation Q1 No operation No operation Example: Q4 No operation Q4 No operation No operation
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE ZERO NZERO Q2 Read register `f'
If skip and followed by 2-word instruction:
If skip and followed by 2-word instruction:
CNT, 1, 0
REG, 1, 0
Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC =
Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO)
Before Instruction PC = After Instruction REG = If REG PC = If REG = PC =
Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO)
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IORLW
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Inclusive OR Literal with W
IORLW k 0 k 255 (W) .OR. k W N, Z 0000 1001 kkkk kkkk The contents of W are ORed with the eight-bit literal `k'. The result is placed in W. 1 1 Q1 Q2 Read literal `k' IORLW 9Ah BFh Q3 Process Data 35h Q4 Write to W
IORWF
Syntax: Operands:
Inclusive OR W with f
IORWF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (W) .OR. (f) dest N, Z 0001 00da ffff ffff Inclusive OR W with register `f'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Q2 Read register `f' IORWF 13h 91h 13h 93h Q3 Process Data RESULT, 0, 1 Q4 Write to destination
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Decode
Example: W = After Instruction W =
Before Instruction Words: Cycles: Q Cycle Activity: Decode
Example:
Before Instruction RESULT = W = After Instruction RESULT = W =
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LFSR
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' MSB Q3 Process Data Q4 Write literal `k' MSB to FSRfH Write literal `k' to FSRfL
Load FSR
LFSR f, k 0f2 0 k 4095 k FSRf None 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk
MOVF
Syntax: Operands:
Move f
MOVF f {,d {,a}} 0 f 255 d [0,1] a [0,1] f dest N, Z 0101 00da ffff ffff The contents of register `f' are moved to a destination dependent upon the status of `d'. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' MOVF = = = = Q3 Process Data REG, 0, 0 22h FFh 22h 22h Q4 Write W
Operation: Status Affected: Encoding: Description:
The 12-bit literal `k' is loaded into the File Select Register pointed to by `f'. 2 2
Decode
Read literal `k' LSB
Process Data
Example: After Instruction FSR2H FSR2L
LFSR 2, 3ABh = = 03h ABh Words: Cycles: Q Cycle Activity:
Example:
Before Instruction REG W After Instruction REG W
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MOVFF
Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description:
Move f to f
MOVFF fs,fd 0 fs 4095 0 fd 4095 (fs) fd None 1100 1111 ffff ffff ffff ffff ffffs ffffd
MOVLB
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move Literal to Low Nibble in BSR
MOVLW k 0 k 255 k BSR None 0000 0001 kkkk kkkk The eight-bit literal `k' is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains `0', regardless of the value of k7:k4. 1 1 Q1 Q2 Read literal `k' MOVLB 02h 05h Q3 Process Data 5 Q4 Write literal `k' to BSR
The contents of source register `fs' are moved to destination register `fd'. Location of source `fs' can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination `fd' can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. 2 2 (3)
Words: Cycles: Q Cycle Activity: Decode
Example:
Before Instruction BSR Register = After Instruction BSR Register =
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f' (src) No operation No dummy read
Q3 Process Data No operation
Q4 No operation Write register `f' (dest)
Decode
Example:
MOVFF = = = =
REG1, REG2 33h 11h 33h 33h
Before Instruction REG1 REG2 After Instruction REG1 REG2
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MOVLW
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' MOVLW W = 5Ah Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register `f' MOVWF 4Fh FFh 4Fh 4Fh Q3 Process Data REG, 0 Q4 Write register `f' Q3 Process Data 5Ah Q4 Write to W 1 1
Move Literal to W
MOVLW k 0 k 255 kW None 0000 1110 kkkk kkkk The eight-bit literal `k' is loaded into W.
MOVWF
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Move W to f
MOVWF 0 f 255 a [0,1] (W) f None 0110 111a ffff ffff Move data from W to register `f'. Location `f' can be anywhere in the 256-byte bank. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 f {,a}
Example: After Instruction
Example: W = REG = After Instruction W REG = =
Before Instruction
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MULLW
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Multiply Literal with W
MULLW k 0 k 255 (W) x k PRODH:PRODL None 0000 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal `k'. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. 1 1 Q1 Q2 Read literal `k' Q3 Process Data Q4 Write registers PRODH: PRODL
MULWF
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Multiply W with f
MULWF 0 f 255 a [0,1] (W) x (f) PRODH:PRODL None 0000 001a ffff ffff An unsigned multiplication is carried out between the contents of W and the register file location `f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and `f' are unchanged. None of the Status flags are affected. Note that neither Overflow nor Carry is possible in this operation. A Zero result is possible but not detected. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Q2 Read register `f' Q3 Process Data Q4 Write registers PRODH: PRODL f {,a}
Words: Cycles: Q Cycle Activity: Decode
Example: Before Instruction W PRODH PRODL After Instruction W PRODH PRODL
MULLW = = = = = =
0C4h E2h ? ? E2h ADh 08h Words: Cycles: Q Cycle Activity: Decode
Example: Before Instruction W REG PRODH PRODL After Instruction W REG PRODH PRODL
MULWF = = = = = = = =
REG, 1 C4h B5h ? ? C4h B5h 8Ah 94h
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NEGF
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Negate f
NEGF f {,a} 0 f 255 a [0,1] (f) + 1 f N, OV, C, DC, Z 0110 110a ffff ffff Location `f' is negated using two's complement. The result is placed in the data memory location `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' NEGF Q3 Process Data REG, 1 Q4 Write register `f'
NOP
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
No Operation
NOP None No operation None 0000 1111 1 1 Q2 No operation Q3 No operation Q4 No operation 0000 xxxx 0000 xxxx 0000 xxxx
No operation.
Example: None.
Words: Cycles: Q Cycle Activity:
Example:
Before Instruction REG = After Instruction REG =
0011 1010 [3Ah] 1100 0110 [C6h]
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POP
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Pop Top of Return Stack
POP None (TOS) bit bucket None 0000 0000 0000 0110 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. 1 1 Q1 Decode Q2 No operation POP GOTO Q3 POP TOS value Q4 No operation
PUSH
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Push Top of Return Stack
PUSH None (PC + 2) TOS None 0000 0000 0000 0101 The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. 1 1 Q1 Decode Q2 PUSH PC + 2 onto return stack PUSH = = = = = 345Ah 0124h 0126h 0126h 345Ah Q3 No operation Q4 No operation
Words: Cycles: Q Cycle Activity:
Words: Cycles: Q Cycle Activity:
Example:
Example: NEW = = = = 0031A2h 014332h 014332h NEW
Before Instruction TOS Stack (1 level down) After Instruction TOS PC
Before Instruction TOS PC After Instruction PC TOS Stack (1 level down)
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RCALL
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Relative Call
RCALL n -1024 n 1023 (PC) + 2 TOS, (PC) + 2 + 2n PC None 1101 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2's complement number `2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2 Q1 Q2 Read literal `n' PUSH PC to stack Q3 Process Data Q4 Write to PC
RESET
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
Reset
RESET None Reset all registers and flags that are affected by a MCLR Reset. All 0000 0000 1111 1111 This instruction provides a way to execute a MCLR Reset in software. 1 1 Q2 Start Reset RESET Reset Value Reset Value Q3 No operation Q4 No operation
Words: Cycles: Q Cycle Activity: Decode
Example: After Instruction Registers = Flags* =
No operation Example:
No operation HERE
No operation RCALL Jump
No operation
Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2)
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RETFIE
Syntax: Operands: Operation:
Return from Interrupt
RETFIE {s} s [0,1] (TOS) PC, 1 GIE/GIEH or PEIE/GIEL; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged GIE/GIEH, PEIE/GIEL 0000 0000 0001 000s Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low-priority global interrupt enable bit. If `s' = 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs. 1 2
RETLW
Syntax: Operands: Operation:
Return Literal to W
RETLW k 0 k 255 k W, (TOS) PC, PCLATU, PCLATH are unchanged None 0000 1100 kkkk kkkk W is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 1 2 Q1 Q2 Read literal `k' No operation Q3 Process Data No operation Q4 POP PC from stack, Write to W No operation
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Decode
Words: Cycles: Q Cycle Activity: Q1 Decode
No operation Example: Q2 Q3 No operation Q4 POP PC from stack Set GIEH or GIEL
No operation
No operation Example:
No operation RETFIE 1
No operation
No operation
After Interrupt PC W BSR STATUS GIE/GIEH, PEIE/GIEL
= = = = =
TOS WS BSRS STATUSS 1
CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; Before Instruction W = After Instruction W =
W contains table offset value W now has table value
W = offset Begin table
End of table
07h value of kn
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RETURN
Syntax: Operands: Operation:
Return from Subroutine
RETURN {s} s [0,1] (TOS) PC; if s = 1, (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged None 0000 0000 0001 001s Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If `s'= 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, STATUS and BSR. If `s' = 0, no update of these registers occurs. 1 2 Q1 Q2 No operation No operation Q3 Process Data No operation Q4 POP PC from stack No operation
RLCF
Syntax: Operands:
Rotate Left f through Carry
RLCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) dest, (f<7>) C, (C) dest<0> C, N, Z 0011 01da ffff ffff The contents of register `f' are rotated one bit to the left through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. C register f
Operation:
Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Decode No operation
Words: Cycles: Q Cycle Activity:
1 1 Q1 Decode Q2 Read register `f' RLCF Q3 Process Data Q4 Write to destination
Example:
RETURN
After Instruction: PC = TOS
Example: Before Instruction REG = C = After Instruction REG = W = C =
REG, 0, 0
1110 0110 0 1110 0110 1100 1100 1
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RLNCF
Syntax: Operands:
Rotate Left f (No Carry)
RLNCF 0 f 255 d [0,1] a [0,1] (f) dest, (f<7>) dest<0> N, Z 0100 01da ffff ffff f {,d {,a}}
RRCF
Syntax: Operands:
Rotate Right f through Carry
RRCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) dest, (f<0>) C, (C) dest<7> C, N, Z 0011 00da ffff ffff The contents of register `f' are rotated one bit to the right through the Carry flag. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. C register f
Operation: Status Affected: Encoding: Description:
Operation:
Status Affected: Encoding: Description:
The contents of register `f' are rotated one bit to the left. If `d' is `0', the result is placed in W. If `d' is `1', the result is stored back in register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f
Words: Cycles: Q Cycle Activity: Q1 Decode
1 1 Q2 Read register `f' RLNCF Q3 Process Data Q4 Write to destination Words: Cycles: Q Cycle Activity: Q1 Decode Q2 1 1
Q3 Process Data REG, 0, 0
Q4 Write to destination
Example: Before Instruction REG = After Instruction REG =
REG, 1, 0 Example:
Read register `f' RRCF
1010 1011 0101 0111
Before Instruction REG = C = After Instruction REG = W = C =
1110 0110 0 1110 0110 0111 0011 0
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RRNCF
Syntax: Operands:
Rotate Right f (No Carry)
RRNCF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f) dest, (f<0>) dest<7> N, Z 0100 00da ffff ffff The contents of register `f' are rotated one bit to the right. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed back in register `f'. If `a' is `0', the Access Bank will be selected, overriding the BSR value. If `a' is `1', then the bank will be selected as per the BSR value. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. register f
SETF
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Set f
SETF f {,a} 0 f 255 a [0,1] FFh f None 0110 100a ffff ffff The contents of the specified register are set to FFh. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Decode Q2 Read register `f' SETF = = 5Ah FFh Q3 Process Data REG, 1 Q4 Write register `f'
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity:
Words: Cycles: Q Cycle Activity: Q1 Decode
1 1 Q2 Read register `f' RRNCF Q3 Process Data REG, 1, 0 Q4 Write to destination Example:
Before Instruction REG After Instruction REG
Example 1:
Before Instruction REG = After Instruction REG = Example 2: W = REG = After Instruction W REG = =
1101 0111 1110 1011 REG, 0, 0
RRNCF
Before Instruction ? 1101 0111 1110 1011 1101 0111
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SLEEP
Syntax: Operands: Operation:
Enter Sleep mode
SLEEP None 00h WDT, 0 WDT postscaler, 1 TO, 0 PD TO, PD 0000 0000 0000 0011 The Power-Down status bit (PD) is cleared. The Time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. 1 1 Q1 Q2 No operation SLEEP Q3 Process Data Q4 Go to Sleep
SUBFWB
Syntax: Operands:
Subtract f from W with Borrow
SUBFWB 0 f 255 d [0,1] a [0,1] (W) - (f) - (C) dest N, OV, C, DC, Z 0101 01da ffff ffff Subtract register `f' and Carry flag (borrow) from W (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored in register `f' . If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Decode
Example: Before Instruction TO = ? PD = ? After Instruction 1 TO = 0 PD =
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register `f'
Q3 Process Data
Q4 Write to destination
If WDT causes wake-up, this bit is cleared.
Example 1: SUBFWB REG, 1, 0 Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative SUBFWB REG, 0, 0 Example 2: Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive SUBFWB REG, 1, 0 Example 3: Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0
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SUBLW
Syntax: Operands: Operation: Status Affected: Encoding: Description Words: Cycles: Q Cycle Activity: Q1 Decode Example 1: Before Instruction W = C = After Instruction W = C = Z = N = Example 2: Before Instruction W = C = After Instruction W = C = Z = N = Example 3: Before Instruction W = C = After Instruction W = C = Z = N = Q2 Read literal `k' SUBLW 01h ? 01h 1 ; result is positive 0 0 SUBLW 02h ? 00h 1 ; result is zero 1 0 SUBLW 03h ? FFh ; (2's complement) 0 ; result is negative 0 1 02h 02h Q3 Process Data 02h Q4 Write to W
Subtract W from Literal
SUBLW k 0 k 255 k - (W) W N, OV, C, DC, Z 0000 1000 kkkk kkkk W is subtracted from the eight-bit literal `k'. The result is placed in W. 1 1
SUBWF
Syntax: Operands:
Subtract W from f
SUBWF 0 f 255 d [0,1] a [0,1] (f) - (W) dest N, OV, C, DC, Z 0101 11da ffff ffff Subtract W from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Q2 Read register `f' SUBWF 3 2 ? 1 2 1 0 0 SUBWF 2 2 ? 2 0 1 1 0 SUBWF 1 2 ? FFh 2 0 0 1 ;(2's complement) ; result is negative Q3 Process Data REG, 1, 0 Q4 Write to destination f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Decode Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N =
; result is positive
REG, 0, 0
; result is zero
REG, 1, 0
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SUBWFB
Syntax: Operands:
Subtract W from f with Borrow
SUBWFB
0 f 255 d [0,1] a [0,1] (f) - (W) - (C) dest N, OV, C, DC, Z 0101 10da ffff ffff
SWAPF
Syntax: Operands:
Swap f
SWAPF f {,d {,a}} 0 f 255 d [0,1] a [0,1] (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> None 0011 10da ffff ffff The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in W. If `d' is `1', the result is placed in register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Q2 Read register `f' SWAPF 53h 35h Q3 Process Data REG, 1, 0 Q4 Write to destination
f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Operation: Status Affected: Encoding: Description:
Subtract W and the Carry flag (borrow) from register `f' (2's complement method). If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode Example 1:
Words: Cycles: Q3 Process Data REG, 1, 0 (0001 1001) (0000 1101) Example: Q4 Write to destination Q Cycle Activity: Decode
Q2 Read register `f' SUBWFB 19h 0Dh 1 0Ch 0Dh 1 0 0
Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W C Z N = = = =
(0000 1011) (0000 1101) ; result is positive
Before Instruction REG = After Instruction REG =
SUBWFB REG, 0, 0 1Bh 1Ah 0 1Bh 00h 1 1 0 SUBWFB 03h 0Eh 1 F5h 0Eh 0 0 1 (0001 1011) (0001 1010) (0001 1011) ; result is zero REG, 1, 0 (0000 0011) (0000 1101)
(1111 0100) ; [2's comp] (0000 1101) ; result is negative
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TBLRD
Syntax: Operands: Operation:
Table Read
TBLRD ( *; *+; *-; +*) None if TBLRD *, (Prog Mem (TBLPTR)) TABLAT, TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT, (TBLPTR) - 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR, (Prog Mem (TBLPTR)) TABLAT
TBLRD
Example 1:
Table Read (Continued)
TBLRD *+ ; = = = = = 55h 00A356h 34h 34h 00A357h
Before Instruction TABLAT TBLPTR MEMORY (00A356h) After Instruction TABLAT TBLPTR Example 2: TBLRD Before Instruction TABLAT TBLPTR MEMORY (01A357h) MEMORY (01A358h) After Instruction TABLAT TBLPTR
+* ; = = = = = = AAh 01A357h 12h 34h 34h 01A358h
Status Affected: None Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +*
Description:
This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment 1 2
Words: Cycles: Q1 Decode No operation
Q Cycle Activity: Q2 No operation No operation (Read Program Memory) Q3 No operation No operation Q4 No operation No operation (Write TABLAT)
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TBLWT
Syntax: Operands: Operation:
Table Write
TBLWT ( *; *+; *-; +*) None if TBLWT*, (TABLAT) Holding Register, TBLPTR - No Change; if TBLWT*+, (TABLAT) Holding Register, (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register, (TBLPTR) - 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR, (TABLAT) Holding Register None 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +*
TBLWT
Example 1:
Table Write (Continued) TBLWT *+;
Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2:
TBLWT +*;
Status Affected: Encoding:
Description:
This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 7.0 "Flash Program Memory" for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment 1 2 Q1 Decode Q2 Q3 Q4
Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h
Words: Cycles: Q Cycle Activity:
No No No operation operation operation
No No No No operation operation operation operation (Read (Write to TABLAT) Holding Register )
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TSTFSZ
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Test f, Skip if 0
TSTFSZ f {,a} 0 f 255 a [0,1] skip if f = 0 None 0110 011a ffff ffff If `f' = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q1 Q2 Read register `f' Q2 No operation Q2 No operation No operation HERE NZERO ZERO = = = = Q3 Process Data Q3 No operation Q3 No operation No operation TSTFSZ : : Q4 No operation Q4 No operation Q4 No operation No operation
XORLW
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Exclusive OR Literal with W
XORLW k 0 k 255 (W) .XOR. k W N, Z 0000 1010 kkkk kkkk The contents of W are XORed with the 8-bit literal `k'. The result is placed in W. 1 1 Q1 Q2 Read literal `k' XORLW B5h 1Ah Q3 Process Data 0AFh Q4 Write to W
Words: Cycles: Q Cycle Activity: Decode
Example: Before Instruction W = After Instruction W =
Words: Cycles:
Q Cycle Activity: Decode If skip: Q1 No operation Q1 No operation No operation Example:
If skip and followed by 2-word instruction:
CNT, 1
Before Instruction PC After Instruction If CNT PC If CNT PC
Address (HERE) 00h, Address (ZERO) 00h, Address (NZERO)
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XORWF
Syntax: Operands:
Exclusive OR W with f
XORWF 0 f 255 d [0,1] a [0,1] (W) .XOR. (f) dest N, Z 0001 10da ffff ffff Exclusive OR the contents of W with register `f'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in the register `f'. If `a' is `0', the Access Bank is selected. If `a' is `1', the BSR is used to select the GPR bank. If `a' is `0' and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 22.2.3 "Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode" for details. 1 1 Q1 Q2 Read register `f' XORWF AFh B5h 1Ah B5h Q3 Process Data REG, 1, 0 Q4 Write to destination f {,d {,a}}
Operation: Status Affected: Encoding: Description:
Words: Cycles: Q Cycle Activity: Decode
Example:
Before Instruction REG = W = After Instruction REG = W =
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22.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F1230/1330 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions. The additional features of the extended instruction set are disabled by default. To enable them, users must set the XINST Configuration bit. The instructions in the extended set (with the exception of CALLW, MOVSF and MOVSS) can all be classified as literal operations, which either manipulate the File Select Registers, or use them for indexed addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: * Dynamic allocation and deallocation of software stack space when entering and leaving subroutines * Function Pointer invocation * Software Stack Pointer manipulation * Manipulation of variables located in a software stack A summary of the instructions in the extended instruction set is provided in Table 22-3. Detailed descriptions are provided in Section 22.2.2 "Extended Instruction Set". The opcode field descriptions in Table 22-1 (page 216) apply to both the standard and extended PIC18 instruction sets. Note: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in the assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler.
22.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets ("[ ]"). This is done to indicate that the argument is used as an index or offset. The MPASMTM Assembler will flag an error if it determines that an index or offset value is not bracketed. When the extended instruction set is enabled, brackets are also used to indicate index arguments in byteoriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 22.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands". Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces ("{ }").
TABLE 22-3:
Mnemonic, Operands ADDFSR ADDULNK CALLW MOVSF MOVSS PUSHL SUBFSR SUBULNK f, k k
EXTENSIONS TO THE PIC18 INSTRUCTION SET
16-Bit Instruction Word Description Add Literal to FSR Add Literal to FSR2 and Return Call Subroutine using WREG Move zs (source) to 1st word fd (destination) 2nd word Move zs (source) to 1st word zd (destination) 2nd word Store Literal at FSR2, Decrement FSR2 Subtract Literal from FSR Subtract Literal from FSR2 and Return Cycles MSb 1 2 2 2 2 1 1 2 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk LSb kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk Status Affected None None None None None None None None
zs, fd zs, zd k f, k k
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22.2.2
ADDFSR
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal `k' Q3 Process Data Q4 Write to FSR
EXTENDED INSTRUCTION SET
Add Literal to FSR
ADDFSR f, k 0 k 63 f [ 0, 1, 2 ] FSR(f) + k FSR(f) None 1110 1000 ffkk kkkk The 6-bit literal `k' is added to the contents of the FSR specified by `f'. 1 1 Status Affected: Encoding: Description:
ADDULNK
Syntax: Operands: Operation:
Add Literal to FSR2 and Return
ADDULNK k 0 k 63 FSR2 + k FSR2, (TOS) PC None 1110 1000 11kk kkkk The 6-bit literal `k' is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. 1 2
Example:
ADDFSR 2, 23h Words: 03FFh 0422h Cycles: Q Cycle Activity: Q1 Decode No Operation Example:
Before Instruction FSR2 = After Instruction FSR2 =
Q2 Read literal `k' No Operation
Q3 Process Data No Operation
Q4 Write to FSR No Operation
ADDULNK 23h 03FFh 0100h 0422h (TOS)
Before Instruction FSR2 = PC = After Instruction FSR2 = PC =
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
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CALLW
Syntax: Operands: Operation:
Subroutine Call Using WREG
CALLW None (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU None 0000 0000 0001 0100 First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, STATUS or BSR. 1 2 Q1 Q2 Read WREG No operation Q3 PUSH PC to stack No operation Q4 No operation No operation
MOVSF
Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description:
Move Indexed to f
MOVSF [zs], fd 0 zs 127 0 fd 4095 ((FSR2) + zs) fd None 1110 1111 1011 ffff 0zzz ffff zzzzs ffffd
Status Affected: Encoding: Description
Words: Cycles: Q Cycle Activity: Decode No operation
The contents of the source register are moved to destination register `fd'. The actual address of the source register is determined by adding the 7-bit literal offset `zs' in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal `fd' in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. 2 2
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2
Q3
Q4 Read source reg Write register `f' (dest)
Example:
HERE
CALLW Decode
Determine Determine source addr source addr No operation No dummy read No operation
Before Instruction PC = PCLATH = PCLATU = W = After Instruction PC = TOS = PCLATH = PCLATU = W =
address (HERE) 10h 00h 06h 001006h address (HERE + 2) 10h 00h 06h Example:
MOVSF = = = = = =
[05h], REG2 80h 33h 11h 80h 33h 33h
Before Instruction FSR2 Contents of 85h REG2 After Instruction FSR2 Contents of 85h REG2
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MOVSS
Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (dest.) Description
Move Indexed to Indexed
MOVSS [zs], [zd] 0 zs 127 0 zd 127 ((FSR2) + zs) ((FSR2) + zd) None 1110 1111 1011 xxxx 1zzz xzzz zzzzs zzzzd
PUSHL
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Store Literal at FSR2, Decrement FSR2
PUSHL k 0k 255 k (FSR2), FSR2 - 1 FSR2 None 1110 1010 kkkk kkkk The 8-bit literal `k' is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. 1 1 Q1 Q2 Read `k' Q3 Process data Q4 Write to destination
The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets `zs' or `zd', respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP. 2 2
Words: Cycles: Q Cycle Activity: Decode
Example:
PUSHL 08h = = = = 01ECh 00h 01EBh 08h
Before Instruction FSR2H:FSR2L Memory (01ECh) After Instruction FSR2H:FSR2L Memory (01ECh)
Words: Cycles: Q Cycle Activity: Q1 Decode Decode
Q2
Q3
Q4 Read source reg Write to dest reg
Determine Determine source addr source addr Determine dest addr Determine dest addr
Example:
MOVSS [05h], [06h] = = = = = = 80h 33h 11h 80h 33h 33h
Before Instruction FSR2 Contents of 85h Contents of 86h After Instruction FSR2 Contents of 85h Contents of 86h
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SUBFSR
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Subtract Literal from FSR
SUBFSR f, k 0 k 63 f [ 0, 1, 2 ] FSR(f - k) FSR(f) None 1110 1001 ffkk kkkk The 6-bit literal `k' is subtracted from the contents of the FSR specified by `f'. 1 1 Q1 Q2 Read register `f' Q3 Process Data Q4 Write to destination
SUBULNK
Syntax: Operands: Operation: Status Affected: Encoding: Description:
Subtract Literal from FSR2 and Return
SUBULNK k 0 k 63 FSR2 - k FSR2, (TOS) PC None 1110 1001 11kk kkkk
Words: Cycles: Q Cycle Activity: Decode
The 6-bit literal `k' is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary `11'); it operates only on FSR2. 1 2
Words: Example: Before Instruction FSR2 = After Instruction FSR2 = Cycles: SUBFSR 2, 23h 03FFh 03DCh Q1 Decode
Q Cycle Activity: Q2 Read register `f' No Operation Q3 Process Data No Operation Q4 Write to destination No Operation
No Operation
Example: Before Instruction FSR2 = PC = After Instruction FSR2 = PC =
SUBULNK 23h 03FFh 0100h 03DCh (TOS)
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22.2.3 BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE
Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely.
22.2.3.1
Extended Instruction Syntax with Standard PIC18 Commands
Note:
In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 6.5.1 "Indexed Addressing with Literal Offset"). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (`a' = 0) or in a GPR bank designated by the BSR (`a' = 1). When the extended instruction set is enabled and `a' = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument - that is, all byte-oriented and bitoriented instructions, or almost half of the core PIC18 instructions - may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 22.2.3.1 "Extended Instruction Syntax with Standard PIC18 Commands"). Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing mode. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types.
When the extended instruction set is enabled, the file register argument, `f', in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value, `k'. As already noted, this occurs only when `f' is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets ("[ ]"). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within brackets, will generate an error in the MPASM Assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing mode, the Access RAM argument is never specified; it will automatically be assumed to be `0'. This is in contrast to standard operation (extended instruction set disabled) when `a' is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler. The destination argument, `d', functions as before. In the latest versions of the MPASM Assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the source listing.
22.2.4
CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET
It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to the PIC18F1230/1330, it is very important to consider the type of code. A large, re-entrant application that is written in `C' and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set.
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ADDWF
Syntax: Operands: Operation: Status Affected: Encoding: Description:
ADD W to Indexed (Indexed Literal Offset mode)
ADDWF 0 k 95 d [0,1] (W) + ((FSR2) + k) dest N, OV, C, DC, Z 0010 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value `k'. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. 1 1 Q1 Q2 Read `k' Q3 Process Data [OFST] , 0 = = = = = = 17h 2Ch 0A00h 20h 37h 20h Q4 Write to destination [k] {,d}
BSF
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
Bit Set Indexed (Indexed Literal Offset mode)
BSF [k], b 0 f 95 0b7 1 ((FSR2) + k) None 1000 bbb0 kkkk kkkk Bit `b' of the register indicated by FSR2, offset by the value `k', is set. 1 1 Q2 Read register `f' BSF = = = = Q3 Process Data Q4 Write to destination
Words: Cycles: Q Cycle Activity:
Example:
[FLAG_OFST], 7 0Ah 0A00h 55h D5h
Decode
Example: W OFST FSR2 Contents of 0A2Ch After Instruction W Contents of 0A2Ch
ADDWF
Before Instruction
Before Instruction FLAG_OFST FSR2 Contents of 0A0Ah After Instruction Contents of 0A0Ah
SETF
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
Set Indexed (Indexed Literal Offset mode)
SETF [k] 0 k 95 FFh ((FSR2) + k) None 0110 1000 kkkk kkkk The contents of the register indicated by FSR2, offset by `k', are set to FFh. 1 1 Q2 Read `k' Q3 Process Data [OFST] 2Ch 0A00h 00h FFh Q4 Write register
Example:
SETF = = = =
Before Instruction OFST FSR2 Contents of 0A2Ch After Instruction Contents of 0A2Ch
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22.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB(R) IDE TOOLS
The latest versions of Microchip's software tools have been designed to fully support the extended instruction set of the PIC18F1230/1330 family of devices. This includes the MPLAB C18 C Compiler, MPASM Assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device. The default setting for the XINST Configuration bit is `0', disabling the extended instruction set and Indexed Literal Offset Addressing mode. For proper execution of applications developed to take advantage of the extended instruction set, XINST must be set during programming. To develop software for the extended instruction set, the user must enable support for the instructions and the Indexed Addressing mode in their language tool(s). Depending on the environment being used, this may be done in several ways: * A menu option, or dialog box within the environment, that allows the user to configure the language tool and its settings for the project * A command line option * A directive in the source code These options vary between different compilers, assemblers and development environments. Users are encouraged to review the documentation accompanying their development systems for the appropriate information.
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23.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings()
Ambient temperature under bias.............................................................................................................-40C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD) 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk byall ports .......................................................................................................................200 mA Maximum current sourced by all ports ..................................................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOL x IOL) 2: Voltage spikes below VSS at the MCLR/VPP/RA5/FLTA pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/ VPP/RA5/FLTA pin, rather than pulling this pin directly to VSS.
NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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FIGURE 23-1: PIC18F1230/1330 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
Voltage
4.2V
40 MHz
Frequency
FIGURE 23-2:
PIC18F1230/1330 VOLTAGE-FREQUENCY GRAPH (EXTENDED)
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
Voltage
4.2V
25 MHz
Frequency
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FIGURE 23-3: PIC18LF1230/1330 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL)
6.0V 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
Voltage
4.2V
4 MHz
40 MHz
Frequency
FMAX = (16.36 MHz/V) (VDDAPPMIN - 2.0V) + 4 MHz Note: VDDAPPMIN is the minimum voltage of the PIC(R) device in the application.
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23.1 DC Characteristics: Supply Voltage PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Supply Voltage PIC18LF1230/1330 PIC18F1230/1330 D001C D001D D002 D003 AVDD AVSS VDR VPOR 2.0 4.2 -- -- -- -- -- -- 5.5 5.5 VDD + 0.3 VSS + 0.3 -- 0.7 V V V V V V See section on Power-on Reset for details HS, XT, RC and LP Oscillator modes Min Typ Max Units Conditions
PIC18LF1230/1330 (Industrial) PIC18F1230/1330 (Industrial, Extended) Param No. D001 Symbol VDD
Analog Supply Voltage VDD - 0.3 Analog Ground Voltage VSS - 0.3 RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset Voltage PIC18LF1230/1330 BORV1:BORV0 = 11 BORV1:BORV0 = 10 2.00 2.65 4.11(2) 4.36 1.5 --
D004
SVDD
0.05
--
--
V/ms See section on Power-on Reset for details
VBOR D005
2.05 2.79 4.33 4.59
2.16 2.93 4.55 4.82
V V V V
D005
All devices BORV1:BORV0 = 01 BORV1:BORV0 = 00
Legend: Note 1: 2:
Shading of rows is to assist in readability of the table. This is the limit to which VDD can be lowered in Sleep mode, or during a device Reset, without losing RAM data. With BOR enabled, full-speed operation (FOSC = 40 MHz) is supported until a BOR occurs. This is valid although VDD may be below the minimum voltage for this frequency.
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23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1230/1330 (Industrial) PIC18F1230/1330 (Industrial, Extended) Param No. Device
Power-Down Current (IPD)(1) PIC18LF1230/1330 100 0.1 0.2 PIC18LF1230/1330 0.1 0.1 0.3 All devices 0.1 0.1 0.4 Extended devices only Note 1: 2: 10 742 0.742 4.80 1.20 1.20 7.80 7.79 7.79 14.8 119 nA A A A A A A A A A -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C VDD = 5.0V (Sleep mode) VDD = 2.0V (Sleep mode) VDD = 3.0V (Sleep mode)
3: 4:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and LVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
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23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1230/1330 (Industrial) PIC18F1230/1330 (Industrial, Extended) Param No. Device Supply Current (IDD)(2) PIC18LF1230/1330
15 15 15
28.1 28.1 28.1 54 54 54 149 149 149 249 0.93 0.93 0.93 1.03 1.03 1.03 2.03 2.03 2.03 3.3
A A A A A A A A A A mA mA mA mA mA mA mA mA mA mA
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C VDD = 5.0V VDD = 3.0V FOSC = 1 MHz (RC_RUN mode, INTOSC source) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 31 kHz (RC_RUN mode, INTRC source) VDD = 2.0V
PIC18LF1230/1330
40 35 30
All devices
105 90 80
Extended devices only
80 0.33 0.33
PIC18LF1230/1330 0.32
PIC18LF1230/1330
0.6 0.55 0.6
All devices
1.1 1.1 1.0
Extended devices only Note 1: 2:
1
3: 4:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and LVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
DS39758D-page 270
2009 Microchip Technology Inc.
PIC18F1230/1330
23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1230/1330 (Industrial) PIC18F1230/1330 (Industrial, Extended) Param No. Device Supply Current (IDD)(2) PIC18LF1230/1330
0.8 0.8 0.8
1.83 1.83 1.83 2.93 2.93 2.93 4.73 4.73 4.73 10.0 7.6 7.6 10.6 10.6 10.6 14.6 15.6 15.6 35.6 179
mA mA mA mA mA mA mA mA mA mA A A A A A A A A A A
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C VDD = 5.0V VDD = 3.0V FOSC = 31 kHz (RC_IDLE mode, INTRC source) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (RC_RUN mode, INTOSC source) VDD = 2.0V
PIC18LF1230/1330
1.3 1.3 1.3
All devices
2.5 2.5 2.5
Extended devices only PIC18LF1230/1330
2.5 2.9 3.1 3.6
PIC18LF1230/1330
4.5 4.8 5.8
All devices
9.2 9.8 11.4
Extended devices only Note 1: 2:
21
3: 4:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and LVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
2009 Microchip Technology Inc.
DS39758D-page 271
PIC18F1230/1330
23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1230/1330 (Industrial) PIC18F1230/1330 (Industrial, Extended) Param No. Device Supply Current (IDD)(2) PIC18LF1230/1330
165 175 190
347 347 347 497 497 497 930 930 930 2.9 497 497 497 830 830 830 1.33 1.33 1.33 5.0
A A A A A A A A A mA A A A A A A mA mA mA mA
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (RC_IDLE mode, INTOSC source) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 1 MHz (RC_IDLE mode, INTOSC source) VDD = 2.0V
PIC18LF1230/1330
250 270 290
All devices
500 520 550
Extended devices only PIC18LF1230/1330
0.6 340 350 360
PIC18LF1230/1330
520 540 580
All devices
1.0 1.1 1.1
Extended devices only Note 1: 2:
1.1
3: 4:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and LVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
DS39758D-page 272
2009 Microchip Technology Inc.
PIC18F1230/1330
23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1230/1330 (Industrial) PIC18F1230/1330 (Industrial, Extended) Param No. Device Supply Current (IDD)(2) PIC18LF1230/1330
250 260 250
497 497 497 750 750 750 3 3 3 3.0 1.93 1.93 1.93 2.93 2.93 2.93 5.93 5.93 5.93 7.0 27.7 27.7 26 25 24 39.3 39.3 39.3
A A A A A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C +125C +125C -40C +25C +85C -40C +25C +85C VDD = 5.0V VDD = 4.2V FOSC = 40 MHz (PRI_RUN, EC oscillator) VDD = 4.2V VDD = 5.0V FOSC = 25 MHz (PRI_RUN, EC oscillator) VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (PRI_RUN, EC oscillator) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 1 MHz (PRI_RUN, EC oscillator) VDD = 2.0V
PIC18LF1230/1330
550 480 460
All devices
1.2 1.1 1.0
Extended devices only
1.0 0.74 0.74
PIC18LF1230/1330 0.72
PIC18LF1230/1330
1.3 1.3 1.3
All devices
2.7 2.6 2.5
Extended devices only Extended devices only
2.6 8.4 11
All devices
15 16 16
All devices
21 21 21
Note 1: 2:
3: 4:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and LVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
2009 Microchip Technology Inc.
DS39758D-page 273
PIC18F1230/1330
23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1230/1330 (Industrial) PIC18F1230/1330 (Industrial, Extended) Param No. Device Supply Current (IDD)(2) All devices
7.5 7.4 7.3
20.3 20.3 20.3 21 20.3 20.3 20.3 21 40 40 40 40 40 40
mA mA mA mA mA mA mA mA mA mA mA mA mA mA
-40C +25C +85C +125C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C VDD = 5.0V VDD = 4.2V FOSC = 10 MHz, 40 MHz internal (PRI_RUN HS+PLL) FOSC = 10 MHz, 40 MHz internal (PRI_RUN HS+PLL) VDD = 5.0V FOSC = 4 MHz, 16 MHz internal (PRI_RUN HS+PLL) VDD = 4.2V FOSC = 4 MHz, 16 MHz internal (PRI_RUN HS+PLL)
Extended devices only All devices
8.0 10 10 9.7
Extended devices only All devices
10 17 17 17
All devices
23 23 23
Note 1: 2:
3: 4:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and LVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
DS39758D-page 274
2009 Microchip Technology Inc.
PIC18F1230/1330
23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1230/1330 (Industrial) PIC18F1230/1330 (Industrial, Extended) Param No. Device Supply Current (IDD)(2) PIC18LF1230/1330
65 65 70
112 112 112 237 237 237 360 360 360 865 427 427 427 740 740 740 1.23 1.23 1.23 1.2 10.7 10.7 9.5 9.0 8.6 17.3 17.3 17.3
A A A A A A A A A A A A A A A A mA mA mA mA mA mA mA mA mA mA mA mA
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C +125C +125C +125C -40C +25C +85C -40C +25C +85C VDD = 5.0V VDD = 4.2V FOSC = 40 MHz (PRI_IDLE mode, EC oscillator) VDD = 4.2V VDD = 5.0V FOSC = 25 MHz (PRI_IDLE mode, EC oscillator) VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (PRI_IDLE mode, EC oscillator) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 1 MHz (PRI_IDLE mode, EC oscillator) VDD = 2.0V
PIC18LF1230/1330
120 120 130
All devices
300 240 300
Extended devices only PIC18LF1230/1330
320 260 255 270
PIC18LF1230/1330
420 430 450
All devices
0.9 0.9 0.9
Extended devices only Extended devices only
1 2.8 4.3
All devices
6.0 6.2 6.6
All devices
8.1 9.1 8.3
Note 1: 2:
3: 4:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and LVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
2009 Microchip Technology Inc.
DS39758D-page 275
PIC18F1230/1330
23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1230/1330 (Industrial) PIC18F1230/1330 (Industrial, Extended) Param No. Device Supply Current (IDD)(2) PIC18LF1230/1330
14 15 16
39.6 39.6 39.6 64 64 64 147 147 147 11.6 11.6 11.6 14.6 14.6 14.6 24.6 24.6 24.6
A A A A A A A A A A A A A A A A A A
-40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 5.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_IDLE mode, Timer1 as clock) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 32 kHz(4) (SEC_RUN mode, Timer1 as clock) VDD = 2.0V
PIC18LF1230/1330
40 35 31
All devices
99 81 75
PIC18LF1230/1330
2.5 3.7 4.5
PIC18LF1230/1330
5.0 5.4 6.3
All devices
8.5 9.0 10.5
Note 1: 2:
3: 4:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and LVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
DS39758D-page 276
2009 Microchip Technology Inc.
PIC18F1230/1330
23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1230/1330 (Industrial) PIC18F1230/1330 (Industrial, Extended) Param No. D022 (IWDT) Device
Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) Watchdog Timer 1.3 1.4 2.0 1.9 2.0 2.8 4.0 5.5 5.6 13 D022A (IBOR) Brown-out Reset
(4)
4.8 5.4 5.4 5.6 6.2 6.2 9.6 9.6 9.6 13 54.6 64.6 44 44 44 37.6 39.6 44.6 54.6 5.5 6.1 6.1 7 7.6 7.6 7.6 7.6 7.6
A A A A A A A A A A A A A A A A A A A A A A A A A A A A
-40C +25C +85C -40C +25C +85C -40C +25C +85C +125C -40C to +85C -40C to +85C -40C to +125C -40C to +85C -40C to +125C -40C to +85C -40C to +85C -40C to +85C -40C to +125C -40C +25C +85C -40C +25C +85C -40C +25C +85C VDD = 5.0V 32 kHz on Timer1(3) VDD = 3.0V 32 kHz on Timer1(3) VDD = 2.0V 32 kHz on Timer1(3) VDD = 2.0V VDD = 3.0V VDD = 5.0V VDD = 5.0V Sleep mode, BOREN1:BOREN0 = 10 VDD = 3.0V VDD = 5.0V VDD = 3.0V VDD = 2.0V
35 40 55 0 0
D022B (ILVD)
Low-Voltage Detect(4)
22 25 29 30
D025 (IOSCB)
Timer1 Oscillator
2.1 1.8 2.1 2.2 2.6 2.9 3.0 3.2 3.4
Note 1: 2:
3: 4:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and LVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
2009 Microchip Technology Inc.
DS39758D-page 277
PIC18F1230/1330
23.2 DC Characteristics: Power-Down and Supply Current PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Typ Max Units Conditions
PIC18LF1230/1330 (Industrial) PIC18F1230/1330 (Industrial, Extended) Param No. D026 (IAD) Device
Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) A/D Converter 1.0 1.0 1.0 2.0 Note 1: 2: 1.6 1.6 1.6 7.6 A A A A -40C to +85C -40C to +85C -40C to +85C -40C to +125C VDD = 2.0V VDD = 3.0V VDD = 5.0V A/D on, not converting
3: 4:
The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VDD or VSS and all features that add delta current disabled (such as WDT, Timer1 oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD or VSS; MCLR = VDD; WDT enabled/disabled as specified. Low-power Timer1 oscillator selected. BOR and LVD enable internal band gap reference. With both modules enabled, current consumption will be less than the sum of both specifications.
DS39758D-page 278
2009 Microchip Technology Inc.
PIC18F1230/1330
23.3 DC Characteristics: PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Input Low Voltage I/O ports: D030 D030A D031 D031A D031B D032 D033 D033A D033B D034 VIH D040 D040A D041 D041A D041B D042 D043 D043A D043B D043C D044 IIL D060 MCLR OSC1 OSC1 OSC1 OSC1 T1CKI Input Leakage Current(2,3) I/O ports -- 200 nA VSS < 5.5V Vss VPIN VDD Pin at high-impedance VSS < 3V Vss VPIN VDD Pin at high-impedance Vss VPIN VDD Vss VPIN VDD VDD = 5V, VPIN = VSS with Schmitt Trigger buffer RC3 and RC4 MCLR OSC1 OSC1 OSC1 T1CKI Input High Voltage I/O ports: with TTL buffer 0.25 VDD + 0.8V 2.0 0.8 VDD 0.7 VDD 2.1 0.8 VDD 0.7 VDD 0.8 VDD 0.9 VDD 1.6 1.6 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD V V V V V V HS, HSPLL modes EC mode RC mode(1) XT, LP modes V V V V I2C enabled I2C enabled VDD < 4.5V 4.5V VDD 5.5V with Schmitt Trigger buffer RC3 and RC4 with TTL buffer VSS -- VSS VSS VSS VSS VSS VSS VSS VSS 0.15 VDD 0.8 0.2 VDD 0.3 VDD 0.8 0.2 VDD 0.3 VDD 0.2 VDD 0.3 0.3 V V V V V V V V V V HS, HSPLL modes RC, EC modes(1) XT, LP modes I2CTM enabled SMBus enabled VDD < 4.5V 4.5V VDD 5.5V Min Max Units Conditions
DC CHARACTERISTICS Param Symbol No. VIL
50
nA
D061 D063 IPU D070 Note 1: 2: IPURB
MCLR OSC1 Weak Pull-up Current PORTB weak pull-up current
-- -- 50
1 1 400
A A A
3:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin.
2009 Microchip Technology Inc.
DS39758D-page 279
PIC18F1230/1330
23.3 DC Characteristics: PIC18F1230/1330 (Industrial) PIC18LF1230/1330 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Output Low Voltage I/O ports OSC2/CLKO (RC, RCIO, EC, ECIO modes) VOH D090 Output High Voltage(3) I/O ports VDD - 0.7 -- V IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C -- -- 0.6 0.6 V V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C Min Max Units Conditions
DC CHARACTERISTICS Param Symbol No. VOL D080 D083
D092
OSC2/CLKO (RC, RCIO, EC, ECIO modes) Capacitive Loading Specs on Output Pins
VDD - 0.7
--
V
D100
COSC2 OSC2 pin
--
15
pF
In XT, HS and LP modes when external clock is used to drive OSC1 To meet the AC Timing Specifications
D101 Note 1: 2:
CIO
All I/O pins and OSC2 (in RC mode)
--
50
pF
3:
In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC(R) device be driven with an external clock while in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin.
DS39758D-page 280
2009 Microchip Technology Inc.
PIC18F1230/1330
TABLE 23-1: MEMORY PROGRAMMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Characteristic Data EEPROM Memory D120 D121 ED VDRW Byte Endurance VDD for Read/Write 100K VMIN 1M -- -- 5.5 E/W -40C to +85C V Using EECON to read/write VMIN = Minimum operating voltage Min Typ Max Units Conditions DC CHARACTERISTICS Param No.
Sym
D122 D123 D124 D125
TDEW
Erase/Write Cycle Time
3.59 40 1M --
4.10 -- 10M 10
4.86 -- -- --
ms Year Provided no other specifications are violated E/W -40C to +85C mA
TRETD Characteristic Retention TREF IDDP Number of Total Erase/Write Cycles before Refresh(1) Supply Current during Programming Program Flash Memory Cell Endurance VDD for Read VDD for Self-Timed Write Self-Timed Write Cycle Time
D130 D131
EP VPR
10K VMIN VMIN 1.79 40 --
100K -- -- 2.05 100 10
-- 5.5 5.5 2.43 -- --
E/W -40C to +85C V V ms Year Provided no other specifications are violated mA VMIN = Minimum operating voltage VMIN = Minimum operating voltage
D132B VPEW D133A TIW D134 D135
TRETD Characteristic Retention IDDP Supply Current during Programming
Data in "Typ" column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Refer to Section 7.8 for a more detailed discussion on data EEPROM endurance.
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TABLE 23-2: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated). Param No. D300 D301 D302 D303 D303A D304 Note 1: TMC2OV Comparator Mode Change to Output Valid Sym VIOFF VICM CMRR TRESP Characteristics Input Offset Voltage Input Common Mode Voltage Common Mode Rejection Ratio Response Time(1) Min -- 0 55 -- -- -- Typ 5.0 -- -- 150 150 -- Max 10 VDD - 1.5 -- 400 600 10 Units mV V dB ns ns s PIC18FXXXX PIC18LFXXXX, VDD = 2.0V Comments
Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from VSS to VDD.
TABLE 23-3:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +125C (unless otherwise stated). Param No. D310 D311 D312 D310 Note 1: Sym VRES VRAA VRUR TSET Characteristics Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time(1) Min VDD/24 -- -- -- Typ -- -- 2k -- Max VDD/32 1/2 -- 10 Units LSb LSb s Comments
Settling time measured while CVRR = 1 and CVR3:CVR0 transitions from `0000' to `1111'.
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FIGURE 23-4: LOW-VOLTAGE DETECT CHARACTERISTICS
VDD (LVDIF can be cleared in software)
VLVD (LVDIF set by hardware)
LVDIF
TABLE 23-4:
LOW-VOLTAGE DETECT CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. D420 Sym Characteristic LVDL<3:0> = 0000 LVD Voltage on VDD Transition High-to-Low LVDL<3:0> = 0001 LVDL<3:0> = 0010 LVDL<3:0> = 0011 LVDL<3:0> = 0100 LVDL<3:0> = 0101 LVDL<3:0> = 0110 LVDL<3:0> = 0111 LVDL<3:0> = 1000 LVDL<3:0> = 1001 LVDL<3:0> = 1010 LVDL<3:0> = 1011 LVDL<3:0> = 1100 LVDL<3:0> = 1101 LVDL<3:0> = 1110 Min 2.06 2.12 2.24 2.32 2.47 2.65 2.74 2.96 3.22 3.37 3.52 3.70 3.90 4.11 4.36 Typ 2.17 2.23 2.36 2.44 2.60 2.79 2.89 3.12 3.39 3.55 3.71 3.90 4.11 4.33 4.59 Max 2.28 2.34 2.48 2.56 2.73 2.93 3.04 3.28 3.56 3.73 3.90 4.10 4.32 4.55 4.82 Units V V V V V V V V V V V V V V V Conditions
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23.4
23.4.1
AC (Timing) Characteristics
TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition 3. TCC:ST 4. Ts T (I2C specifications only) (I2C specifications only) Time
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T13CKI WR
P R V Z High Low
Period Rise Valid High-impedance High Low
SU STO
Setup Stop condition
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23.4.2 TIMING CONDITIONS
Note: The temperature and voltages specified in Table 23-5 apply to all timing specifications unless otherwise noted. Figure 23-5 specifies the load conditions for the timing specifications. Because of space limitations, the generic terms "PIC18FXXXX" and "PIC18LFXXXX" are used throughout this section to refer to the PIC18F1230/1330 and PIC18LF1230/ 1330 families of devices specifically and only those devices.
TABLE 23-5:
TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 23.1 and Section 23.3. LF parts operate for industrial temperatures only.
AC CHARACTERISTICS
FIGURE 23-5:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 VDD/2 Pin VSS Pin VSS RL = 464 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports CL CL Load Condition 2
RL
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23.4.3 TIMING DIAGRAMS AND SPECIFICATIONS EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL)
Q4 Q1 Q2 Q3 Q4 Q1
FIGURE 23-6:
OSC1
1 2 3 3 4 4
CLKO
TABLE 23-6:
Param. No. 1A
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic External CLKI Frequency(1) Min DC DC DC Oscillator Frequency
(1)
Symbol FOSC
Max 1 40 31.25 4 4 20 200 -- -- -- -- 1 250 250 200 -- -- -- -- -- 20 50 7.5
Units MHz MHz kHz MHz MHz MHz kHz ns ns ns ns s ns ns s ns ns ns s ns ns ns ns
Conditions XT, RC Oscillator modes EC Oscillator mode LP Oscillator mode RC Oscillator mode XT Oscillator mode HS Oscillator mode LP Oscillator mode XT, RC Oscillator modes HS Oscillator mode EC Oscillator mode RC Oscillator mode XT Oscillator mode HS Oscillator mode HS +PLL Oscillator mode LP Oscillator mode TCY = 4/FOSC, Industrial TCY = 4/FOSC, Extended XT Oscillator mode LP Oscillator mode HS Oscillator mode XT Oscillator mode LP Oscillator mode HS Oscillator mode
DC 0.1 4 5
1
TOSC
External CLKI Period(1)
1000 50 25
Oscillator Period
(1)
250 250 50 100 5
2 3
TCY TOSL, TOSH TOSR, TOSF
Instruction Cycle
Time(1)
100 160 30 2.5 10 -- -- --
External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time
4
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
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TABLE 23-7:
Param No. F10 F11 F12 F13 Sym
PLL CLOCK TIMING SPECIFICATIONS (VDD = 4.2V TO 5.5V)
Characteristic Min 4 16 -- -2 Typ -- -- -- -- Max 10 40 2 +2 Units Conditions
FOSC Oscillator Frequency Range FSYS On-Chip VCO System Frequency trc CLK PLL Start-up Time (Lock Time) CLKO Stability (Jitter)
MHz HS mode only MHz HS mode only ms %
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
TABLE 23-8:
AC CHARACTERISTICS: INTERNAL RC ACCURACY
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended
Param No. Device Min Typ Max Units Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz, 31 kHz(1) PIC18LF1230/1330 -2 -5 -10 PIC18F1230/1330 -2 -5 -10 INTRC Accuracy @ Freq = 31 kHz(2,3) PIC18LF1230/1330 26.562 PIC18F1230/1330 26.562 Legend: Note 1: 2: 3: -- -- 35.938 35.938 kHz kHz -40C to +85C -40C to +85C VDD = 2.7-3.3V VDD = 4.5-5.5V +/-1 -- +/-1 +/-1 -- +/-1 2 5 10 2 5 10 % % % % % % +25C -10C to +85C -40C to +85C +25C -10C to +85C -40C to +85C VDD = 2.7-3.3V VDD = 2.7-3.3V VDD = 2.7-3.3V VDD = 4.5-5.5V VDD = 4.5-5.5V VDD = 4.5-5.5V
Shading of rows is to assist in readability of the table. Frequency calibrated at 25C. OSCTUNE register can be used to compensate for temperature drift. INTRC frequency after calibration. Change of INTRC frequency as VDD changes.
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FIGURE 23-7: CLKO AND I/O TIMING
Q4 OSC1 10 CLKO 13 I/O pin (Input) 17 I/O pin (Output) Old Value 20, 21 Note: Refer to Figure 23-5 for load conditions. 15 New Value 14 19 18 12 16 11 Q1 Q2 Q3
TABLE 23-9:
Param No. 10 11 12 13 14 15 16 17 18 18A 19 20 20A 21 21A 22 23 TINP TRBP TioF TioV2osH TioR Symbol TosH2ckL TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI
CLKO AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKO CLKO Rise Time CLKO Fall Time CLKO to Port Out Valid Port In Valid before CLKO Port In Hold after CLKO OSC1 (Q1 cycle) to Port Out Valid OSC1 (Q2 cycle) to Port PIC18FXXXX Input Invalid (I/O in hold time) PIC18LFXXXX Port Input Valid to OSC1 (I/O in setup time) Port Output Rise Time Port Output Fall Time INTx Pin High or Low Time RB7:RB4 Change INTx High or Low Time PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX Min -- -- -- -- -- 0.25 TCY + 25 0 -- 100 200 0 -- -- -- -- TCY TCY Typ 75 75 35 35 -- -- -- 50 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 0.5 TCY + 20 -- -- 150 -- -- -- 25 60 25 60 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VDD = 2.0V VDD = 2.0V VDD = 2.0V (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TosH2ckH OSC1 to CLKO
These parameters are asynchronous events not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKO output is 4 x TOSC.
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FIGURE 23-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR PWRT Time-out Oscillator Time-out Internal Reset Watchdog Timer Reset 34 I/O pins Note: Refer to Figure 23-5 for load conditions. 33 32 30
31
34
FIGURE 23-9:
BROWN-OUT RESET TIMING
VDD BVDD 35 VIRVST
Enable Internal Reference Voltage Internal Reference Voltage Stable
36
TABLE 23-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS
Param. Symbol No. 30 31 32 33 34 35 36 37 38 39 TmcL TWDT TOST TPWRT TIOZ TBOR TIRVST TLVD TCSD TIOBST Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (no postscaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-Impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Time for Internal Reference Voltage to become Stable Low-Voltage Detect Pulse Width CPU Start-up Time Time for INTOSC to Stabilize Min 2 3.4 1024 TOSC 55.6 -- 200 -- 200 -- -- Typ -- 4.0 -- 65.5 2 -- 20 -- 10 1 Max -- 4.6 1024 TOSC 75 -- -- 50 -- -- -- Units s ms -- ms s s s s s s VDD VLVD VDD BVDD (see D005) TOSC = OSC1 period Conditions
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FIGURE 23-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40 42 T1OSO/T1CKI
41
45 47 TMR0 or TMR1 Note: Refer to Figure 23-5 for load conditions.
46 48
TABLE 23-11: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param No. 40 41 42 Symbol Tt0H Tt0L Tt0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No prescaler With prescaler No prescaler With prescaler No prescaler With prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 10 Greater of: 20 ns or (TCY + 40)/N 0.5 TCY + 20 10 25 30 50 0.5 TCY + 5 10 25 30 50 Greater of: 20 ns or (TCY + 40)/N 60 DC 2 TOSC Max -- -- -- -- -- -- Units ns ns ns ns ns ns N = prescale value (1, 2, 4,..., 256) Conditions
45
Tt1H
T1CKI High Time
Synchronous, no prescaler Synchronous, with prescaler Asynchronous PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns VDD = 2.0V N = prescale value (1, 2, 4, 8) VDD = 2.0V VDD = 2.0V VDD = 2.0V
46
Tt1L
T1CKI Low Time
Synchronous, no prescaler Synchronous, with prescaler Asynchronous PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX
47
Tt1P
T1CKI Input Period
Synchronous
Asynchronous Ft1 48 T1CKI Oscillator Input Frequency Range Tcke2tmrI Delay from External T1CKI Clock Edge to Timer Increment
-- 50 7 TOSC
ns kHz --
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FIGURE 23-11:
RA2/TX/CK pin 121 RA3/RX/DT pin 120 Note: Refer to Figure 23-5 for load conditions. 122 121
EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 23-12: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param No. 120 Symbol Characteristic Min Max Units Conditions
TckH2dtV SYNC XMIT (MASTER & SLAVE) Clock High to Data Out Valid Tckrf Tdtrf Clock Out Rise Time and Fall Time (Master mode) Data Out Rise Time and Fall Time
PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX
-- -- -- -- -- --
40 100 20 50 20 50
ns ns ns ns ns ns VDD = 2.0V VDD = 2.0V VDD = 2.0V
121 122
FIGURE 23-12:
RA2/TX/CK pin RA3/RX/DT pin
EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
125
126 Note: Refer to Figure 23-5 for load conditions.
TABLE 23-13: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS
Param. No. 125 126 Symbol TdtV2ckl TckL2dtl Characteristic SYNC RCV (MASTER & SLAVE) Data Hold before CK (DT hold time) Data Hold after CK (DT hold time) Min Max Units Conditions
10 15
-- --
ns ns
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TABLE 23-14: A/D CONVERTER CHARACTERISTICS
Param Symbol No. A01 A03 A04 A06 A07 A10 A20 A21 A22 A25 A30 A50 NR EIL EDL EOFF EGN -- VREF VREF+ VREFVAIN ZAIN IREF Characteristic Resolution Integral Linearity Error Differential Linearity Error Offset Error Gain Error Monotonicity Reference Voltage Range (VREF+ - VSS) Positive Reference Voltage Negative Reference Voltage Analog Input Voltage Recommended Impedance of Analog Voltage Source VREF+ Input Current(2) 1.8 3 VSS VSS - 0.3V VREF-- -- -- Min -- -- -- -- -- Typ -- -- -- -- -- Guaranteed(1) -- -- -- -- -- -- -- -- -- -- VREF+ VDD - 3.0V VREF+ 2.5 5 150 Max 10 < 1 < 1 < 2 < 1 Units bit Conditions VREF 3.0V
LSb VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V LSb VREF 3.0V -- V V V -- V k A A During VAIN acquisition. During A/D conversion cycle. VSS VAIN VREF VDD 3.0V VDD 3.0V
Note 1: 2:
The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. VREF+ current is from RA4/T0CKI/AN2/VREF+ pin or VDD, whichever is selected as the VREF+ source.
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FIGURE 23-13: A/D CONVERSION TIMING
BSF ADCON0, GO (Note 2) Q4 A/D CLK
(1)
131 130
132 9 8 7
A/D DATA
...
...
2
1
0
ADRES ADIF GO SAMPLE
OLD_DATA
NEW_DATA TCY DONE
SAMPLING STOPPED
Note
1: 2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 23-15: A/D CONVERSION REQUIREMENTS
Param Symbol No. 130 TAD Characteristic A/D Clock Period PIC18FXXXX PIC18LFXXXX PIC18FXXXX PIC18LFXXXX 131 132 135 136 Note 1: 2: 3: 4: TCNV TACQ TSWC TDIS Conversion Time (not including acquisition time)(2) Acquisition Time(3) Switching Time from Convert Sample Discharge Time Min 0.7 1.4 -- -- 11 1.4 -- 0.2 Max 25.0(1) 25.0(1) 1 3 12 -- (Note 4) -- s Units s s s s TAD s -40C to +85C Conditions TOSC based, VREF 3.0V VDD = 2.0V, TOSC based, VREF full range A/D RC mode VDD = 2.0V, A/D RC mode
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. ADRES register may be read on the following TCY cycle. The time for the holding capacitor to acquire the "New" input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50. On the following cycle of the device clock.
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NOTES:
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24.0
24.1
PACKAGING INFORMATION
Package Marking Information
18-Lead PDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC18F1330-I/P e3 0910017
18-Lead SOIC
XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example
PIC18F1230E/SO e3 0910017
20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example PIC18F1230E/SS e3 0910017
28-Lead QFN
Example
XXXXXXXX XXXXXXXX YYWWNNN
18F1330 -I/ML e3 0910017
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
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24.2 Package Details
The following sections give the technical details of the packages.
18-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
N NOTE 1
E1
1
2
3 D E
A
A2 L A1 b1 b e
Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .115 .015 .300 .240 .880 .115 .008 .045 .014 - MIN INCHES NOM 18 .100 BSC - .130 - .310 .250 .900 .130 .010 .060 .018 - .210 .195 - .325 .280 .920 .150 .014 .070 .022 MAX
c
eB
.430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-007B
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18-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1 NOTE 1 1 23 e b h c
h
A
A2
A1
L L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.20 0.31 5 5 0.25 0.40 - 2.05 0.10 MIN
MILLIMETERS NOM 18 1.27 BSC - - - 10.30 BSC 7.50 BSC 11.55 BSC - - 1.40 REF - - - - - 8 0.33 0.51 15 0.75 1.27 2.65 - 0.30 MAX
15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-051B
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1RWH
)RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ
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20-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1
NOTE 1 12 e b c
A
A2
A1 L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Lead Thickness Foot Angle Lead Width N e A A2 A1 E E1 D L L1 c b 0.09 0 0.22 - 1.65 0.05 7.40 5.00 6.90 0.55 MIN MILLIMETERS NOM 20 0.65 BSC - 1.75 - 7.80 5.30 7.20 0.75 1.25 REF - 4 - 0.25 8 0.38 2.00 1.85 - 8.20 5.60 7.50 0.95 MAX
L
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-072B
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28-Lead Plastic Quad Flat, No Lead Package (ML) - 6x6 mm Body [QFN] with 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D2
EXPOSED PAD
e E E2 2 1 2 1 N NOTE 1 TOP VIEW BOTTOM VIEW L K b
N
A
A3
A1
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length Contact-to-Exposed Pad N e A A1 A3 E E2 D D2 b L K 3.65 0.23 0.50 0.20 3.65 0.80 0.00 MIN MILLIMETERS NOM 28 0.65 BSC 0.90 0.02 0.20 REF 6.00 BSC 3.70 6.00 BSC 3.70 0.30 0.55 - 4.20 0.35 0.70 - 4.20 1.00 0.05 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-105B
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/HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ [ PP %RG\ >4)1@ ZLWK PP &RQWDFW /HQJWK
1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ
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NOTES:
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APPENDIX A: REVISION HISTORY
Revision C (March 2007)
Updated Section 23.0 "Electrical Characteristics" and Section 24.0 "Packaging Information".
Revision A (November 2005)
Original data sheet for PIC18F1230/1330 devices.
Revision D (November 2009)
Updated LIN 1.2 to LIN/J2602 throughout document along with minor corrections throughout document. Added the PIC18LF1230 and PIC18LF1330 devices. Refer to Table A-1 for additional revision history.
Revision B (February 2006)
Data bank information was updated and a note was added for calculating the PCPWM duty cycle.
TABLE A-1:
SECTION REVISION HISTORY
Section Name Update Description Updated Table 1-2 Updated Table 6-2 Updated Section 7.2.4 "Table Pointer Boundaries", Figure 7-3 Updated Section 8.2 "EECON1 and EECON2 Registers", Section 8.8 "Using the Data EEPROM" Updated Section 10.2 "PORTB, TRISB and LATB Registers" Updated Register 14-6, Section 14.11.2 "Output Polarity Control" Updated Register 15-3, Section 15.1 "Baud Rate Generator (BRG)", Table 15-2, Section 15.1.3 "Auto-Baud Rate Detect", Section 15.2 "EUSART Asynchronous Mode", Table 15-5, Table 15-6, Section 15.3 "EUSART Synchronous Master Mode", Figure 15-11, Table 15-7, Figure 15-13, Table 15-8, Table 15-9, Table 15-10 Updated Register 16-2 Updated Figure 17-2 Updated Section 18.1 "Configuring the Comparator Voltage Reference", Register 18-1, Figure 18-1 Updated Register 20-6, Register 20-13, Register 20-14 Updated Table 22-2 Updated Table 23-1, Figure 23-3, Table 23-2, Table 23-3, Table 234, Table 23-5, Table 23-6, Table 23-8, Table 23-14, Table 23-15
Section 1.0 "Device Overview" Section 6.0 "Memory Organization" Section 7.0 "Flash Program Memory" Section 8.0 "Data EEPROM Memory" Section 10.0 "I/O Ports" Section 14.0 "Power Control PWM Module" Section 15.0 "Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)"
Section 16.0 "10-Bit Analog-to-Digital Converter (A/D) Module" Section 17.0 "Comparator Module" Section 18.0 "Comparator Voltage Reference Module" Section 20.0 "Special Features of the CPU" Section 22.0 "Instruction Set Summary" Section 23.0 "Electrical Characteristics"
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APPENDIX B: DEVICE DIFFERENCES
The differences between the devices listed in this data sheet are shown in Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
Features PIC18F1230 4096 2048 18-Pin PDIP 18-Pin SOIC 20-Pin SSOP 28-Pin QFN PIC18F1330 8192 4096 18-Pin PDIP 18-Pin SOIC 20-Pin SSOP 28-Pin QFN
Program Memory (Bytes) Program Memory (Instructions) Packages
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APPENDIX C: CONVERSION CONSIDERATIONS APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES
This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable
This section discusses how to migrate from a Baseline device (i.e., PIC16C5X) to an Enhanced MCU device (i.e., PIC18FXXX). The following are the list of modifications over the PIC16C5X microcontroller family: Not Currently Available
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APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES APPENDIX F: MIGRATION FROM HIGH-END TO ENHANCED DEVICES
A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the Enhanced devices (i.e., PIC18FXXX) is provided in AN716, "Migrating Designs from PIC16C74A/74B to PIC18C442". The changes discussed, while device specific, are generally applicable to all mid-range to Enhanced device migrations. This Application Note is available as Literature Number DS00716.
A detailed discussion of the migration pathway and differences between the high-end MCU devices (i.e., PIC17CXXX) and the Enhanced devices (i.e., PIC18FXXX) is provided in AN726, "PIC17CXXX to PIC18CXXX Migration". This Application Note is available as Literature Number DS00726.
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INDEX
A
A/D ................................................................................... 169 A/D Converter Interrupt, Configuring ....................... 173 Acquisition Requirements ........................................ 174 ADCON0 Register .................................................... 169 ADCON1 Register .................................................... 169 ADCON2 Register .................................................... 169 ADRESH Register ............................................ 169, 172 ADRESL Register .................................................... 169 Analog Port Pins, Configuring .................................. 176 Associated Registers ............................................... 178 Configuring the Module ............................................ 173 Conversion Clock (TAD) ........................................... 175 Conversion Requirements ....................................... 293 Conversion Status (GO/DONE Bit) .......................... 172 Conversions ............................................................. 177 Converter Characteristics ........................................ 292 Discharge ................................................................. 177 Operation in Power-Managed Modes ...................... 176 Selecting and Configuring Acquisition Time ............ 175 Triggering Conversions ............................................ 174 Absolute Maximum Ratings ............................................. 265 AC (Timing) Characteristics ............................................. 284 Conditions ................................................................ 285 Load Conditions for Device Timing Specifications ... 285 Parameter Symbology ............................................. 284 Temperature and Voltage Specifications ................. 285 AC Characteristics Internal RC Accuracy ............................................... 287 Access Bank Mapping with Indexed Literal Offset Addressing Mode .. 69 Remapping with Indexed Literal Offset Addressing Mode ............................................................................ 69 ADCON0 Register ............................................................ 169 GO/DONE Bit ........................................................... 172 ADCON1 Register ............................................................ 169 ADCON2 Register ............................................................ 169 ADDFSR .......................................................................... 258 ADDLW ............................................................................ 221 ADDULNK ........................................................................ 258 ADDWF ............................................................................ 221 ADDWFC ......................................................................... 222 ADRESH Register ............................................................ 169 ADRESL Register .................................................... 169, 172 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 222 ANDWF ............................................................................ 223 Assembler MPASM Assembler .................................................. 212 External Power-on Reset Circuit (Slow VDD Power-up) 41 Fail-Safe Clock Monitor ........................................... 205 Generic I/O Port ......................................................... 87 Interrupt Logic ............................................................ 94 Low-Voltage Detect ................................................. 188 On-Chip Reset Circuit ................................................ 39 PIC18F1230/1330 ..................................................... 12 PLL (HS Mode) .......................................................... 23 Power Control PWM ................................................ 118 PWM (One Output Pair, Complementary Mode) ..... 119 PWM (One Output Pair, Independent Mode) .......... 119 PWM I/O Pin ............................................................ 142 PWM Time Base ...................................................... 121 Reads From Flash Program Memory ........................ 75 Single Comparator ................................................... 180 Table Read Operation ............................................... 71 Table Write Operation ............................................... 72 Table Writes to Flash Program Memory .................... 77 Timer0 in 16-Bit Mode ............................................. 108 Timer0 in 8-Bit Mode ............................................... 108 Timer1 ..................................................................... 112 Timer1 (16-Bit Read/Write Mode) ............................ 112 Watchdog Timer ...................................................... 202 BN .................................................................................... 224 BNC ................................................................................. 225 BNN ................................................................................. 225 BNOV .............................................................................. 226 BNZ ................................................................................. 226 BOR. See Brown-out Reset. BOV ................................................................................. 229 BRA ................................................................................. 227 Brown-out Reset (BOR) ..................................................... 42 Detecting ................................................................... 42 Disabling in Sleep Mode ............................................ 42 Software Enabled ...................................................... 42 BSF .................................................................................. 227 BTFSC ............................................................................. 228 BTFSS ............................................................................. 228 BTG ................................................................................. 229 BZ .................................................................................... 230
C
C Compilers MPLAB C18 ............................................................. 212 MPLAB C30 ............................................................. 212 CALL ................................................................................ 230 CALLW ............................................................................ 259 Clock Sources .................................................................... 26 Selecting the 31 kHz Source ..................................... 27 Selection Using OSCCON Register .......................... 27 CLRF ............................................................................... 231 CLRWDT ......................................................................... 231 Code Examples 16 x 16 Signed Multiply Routine ................................ 86 16 x 16 Unsigned Multiply Routine ............................ 86 8 x 8 Signed Multiply Routine .................................... 85 8 x 8 Unsigned Multiply Routine ................................ 85 Computed GOTO Using an Offset Value .................. 54 Data EEPROM Read ................................................. 83 Data EEPROM Refresh Routine ............................... 84 Data EEPROM Write ................................................. 83 Erasing a Flash Program Memory Row ..................... 76 Fast Register Stack ................................................... 54
B
BC .................................................................................... 223 BCF .................................................................................. 224 Block Diagrams A/D ........................................................................... 172 Analog Input Model .................................................. 173 Comparator Analog Input Model .............................. 181 Comparator Voltage Reference ............................... 185 Dead-Time Control Unit for One PWM Output Pair . 135 Device Clock .............................................................. 26 EUSART Receive .................................................... 160 EUSART Transmit ................................................... 158
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How to Clear RAM (Bank 0) Using Indirect Addressing . 65 Implementing a Real-Time Clock Using a Timer1 Interrupt Service ...................................................... 115 Initializing PORTA ...................................................... 87 Initializing PORTB ...................................................... 90 Reading a Flash Program Memory Word .................. 75 Saving STATUS, WREG and BSR Registers in RAM ... 105 Writing to Flash Program Memory ....................... 78-79 Code Protection ....................................................... 191, 207 Associated Registers ............................................... 207 Configuration Register Protection ............................ 210 Data EEPROM ......................................................... 210 Program Memory ..................................................... 208 COMF ............................................................................... 232 Comparator ...................................................................... 179 Analog Input Connection Considerations ................. 181 Associated Registers ............................................... 182 Configuration ............................................................ 180 Effects of a Reset ..................................................... 181 Interrupts .................................................................. 180 Operation ................................................................. 180 Operation During Sleep ........................................... 181 Outputs .................................................................... 180 Reference ................................................................ 180 Response Time ........................................................ 180 Comparator Specifications ............................................... 282 Comparator Voltage Reference ....................................... 183 Accuracy and Error .................................................. 185 Associated Registers ............................................... 185 Configuring ............................................................... 183 Effects of a Reset ..................................................... 185 Operation During Sleep ........................................... 185 Computed GOTO ............................................................... 54 Configuration Bits ............................................................. 191 Context Saving During Interrupts ..................................... 105 Conversion Considerations .............................................. 305 CPFSEQ .......................................................................... 232 CPFSGT ........................................................................... 233 CPFSLT ........................................................................... 233 Crystal Oscillator/Ceramic Resonator ................................ 21 Customer Change Notification Service ............................ 314 Customer Notification Service .......................................... 314 Customer Support ............................................................ 314 Data Memory ..................................................................... 57 Access Bank .............................................................. 59 and the Extended Instruction Set .............................. 67 Bank Select Register (BSR) ...................................... 57 General Purpose Registers ....................................... 59 Map for PIC18F1230/1330 ........................................ 58 Special Function Registers ........................................ 60 DAW ................................................................................ 234 DC Characteristics ........................................................... 279 Power-Down and Supply Current ............................ 269 Supply Voltage ........................................................ 268 DCFSNZ .......................................................................... 235 DECF ............................................................................... 234 DECFSZ .......................................................................... 235 Development Support ...................................................... 211 Device Differences ........................................................... 304 Device Overview .................................................................. 9 Details on Individual Family Members ....................... 10 Features (table) ......................................................... 11 New Core Features ...................................................... 9 Other Special Features .............................................. 10 Device Reset Timers ......................................................... 43 Oscillator Start-up Timer (OST) ................................. 43 PLL Lock Time-out ..................................................... 43 Power-up Timer (PWRT) ........................................... 43 Time-out Sequence ................................................... 43 Direct Addressing .............................................................. 66
E
Effect on Standard PIC MCU Instructions ....................... 262 Effects of Power-Managed Modes on Various Clock Sources 29 Electrical Characteristics ................................................. 265 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART). See EUSART. Equations A/D Acquisition Time ............................................... 174 A/D Minimum Charging Time ................................... 174 Calculating the Minimum Required Acquisition Time .... 174 PWM Frequency ...................................................... 129 PWM Period for Continuous Up/Down Count Mode 129 PWM Period for Free-Running Mode ...................... 129 PWM Resolution ...................................................... 129 Errata ................................................................................... 7 EUSART Asynchronous Mode ................................................ 157 12-Bit Break Character Sequence ................... 163 Associated Registers, Receive ........................ 161 Associated Registers, Transmit ....................... 159 Auto-Wake-up on Sync Break Character ........ 161 Receiver .......................................................... 160 Receiving a Break Character ........................... 163 Setting Up 9-Bit Mode with Address Detect .... 160 Transmitter ...................................................... 157 Baud Rate Generator Operation in Power-Managed Modes .............. 151 Baud Rate Generator (BRG) ................................... 151 Associated Registers ....................................... 152 Auto-Baud Rate Detect .................................... 155 Baud Rate Error, Calculating ........................... 152 Baud Rates, Asynchronous Modes ................. 153 High Baud Rate Select (BRGH Bit) ................. 151 Sampling .......................................................... 151 Synchronous Master Mode ...................................... 164 Associated Registers, Receive ........................ 166
D
Data Addressing Modes ..................................................... 65 Comparing Options with the Extended Instruction Set Enabled .............................................................. 68 Direct .......................................................................... 65 Indexed Literal Offset ................................................. 67 Instructions Affected .......................................... 67 Indirect ....................................................................... 65 Inherent and Literal .................................................... 65 Data EEPROM Memory ..................................................... 81 Associated Registers ................................................. 84 EEADR Register ........................................................ 81 EECON1 and EECON2 Registers ............................. 81 Operation During Code-Protect ................................. 84 Protection Against Spurious Write ............................. 83 Reading ...................................................................... 83 Using .......................................................................... 84 Write Verify ................................................................ 83 Writing ........................................................................ 83
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Associated Registers, Transmit ....................... 165 Reception ......................................................... 166 Transmission ................................................... 164 Synchronous Slave Mode ........................................ 167 Associated Registers, Receive ........................ 168 Associated Registers, Transmit ....................... 167 Reception ......................................................... 168 Transmission ................................................... 167 Extended Instruction Set ADDFSR .................................................................. 258 ADDULNK ................................................................ 258 and Using MPLAB Tools .......................................... 264 CALLW ..................................................................... 259 Considerations for Use ............................................ 262 MOVSF .................................................................... 259 MOVSS .................................................................... 260 PUSHL ..................................................................... 260 SUBFSR .................................................................. 261 SUBULNK ................................................................ 261 Syntax ...................................................................... 257 External Clock Input ........................................................... 22
I
I/O Ports ............................................................................ 87 ID Locations ............................................................. 191, 210 INCF ................................................................................ 236 INCFSZ ............................................................................ 237 In-Circuit Debugger .......................................................... 210 In-Circuit Serial Programming (ICSP) ...................... 191, 210 Independent PWM Mode Duty Cycle Assignment ........................................... 137 Output ...................................................................... 137 Output, Channel Override ........................................ 138 Indexed Literal Offset Addressing and Standard PIC18 Instructions ............................. 262 Indexed Literal Offset Mode ............................................. 262 Indirect Addressing ............................................................ 66 INFSNZ ............................................................................ 237 Initialization Conditions for all Registers ...................... 47-50 Instruction Cycle ................................................................ 55 Clocking Scheme ....................................................... 55 Flow/Pipelining .......................................................... 55 Instruction Set .................................................................. 215 ADDLW .................................................................... 221 ADDWF ................................................................... 221 ADDWF (Indexed Literal Offset Mode) .................... 263 ADDWFC ................................................................. 222 ANDLW .................................................................... 222 ANDWF ................................................................... 223 BC ............................................................................ 223 BCF ......................................................................... 224 BN ............................................................................ 224 BNC ......................................................................... 225 BNN ......................................................................... 225 BNOV ...................................................................... 226 BNZ ......................................................................... 226 BOV ......................................................................... 229 BRA ......................................................................... 227 BSF .......................................................................... 227 BSF (Indexed Literal Offset Mode) .......................... 263 BTFSC ..................................................................... 228 BTFSS ..................................................................... 228 BTG ......................................................................... 229 BZ ............................................................................ 230 CALL ........................................................................ 230 CLRF ....................................................................... 231 CLRWDT ................................................................. 231 COMF ...................................................................... 232 CPFSEQ .................................................................. 232 CPFSGT .................................................................. 233 CPFSLT ................................................................... 233 DAW ........................................................................ 234 DCFSNZ .................................................................. 235 DECF ....................................................................... 234 DECFSZ .................................................................. 235 Extended Instruction Set ......................................... 257 General Format ....................................................... 217 GOTO ...................................................................... 236 INCF ........................................................................ 236 INCFSZ .................................................................... 237 INFSNZ .................................................................... 237 IORLW ..................................................................... 238 IORWF ..................................................................... 238 LFSR ....................................................................... 239 MOVF ...................................................................... 239 MOVFF .................................................................... 240 MOVLB .................................................................... 240
F
Fail-Safe Clock Monitor ............................................ 191, 205 Exiting Operation ..................................................... 205 Interrupts in Power-Managed Modes ....................... 206 POR or Wake From Sleep ....................................... 206 WDT During Oscillator Failure ................................. 205 Fast Register Stack ............................................................ 54 Firmware Instructions ....................................................... 215 Flash Program Memory ..................................................... 71 Associated Registers ................................................. 79 Control Registers ....................................................... 72 EECON1 and EECON2 ..................................... 72 TABLAT (Table Latch) Register ......................... 74 TBLPTR (Table Pointer) Register ...................... 74 Erase Sequence ........................................................ 76 Erasing ....................................................................... 76 Operation During Code-Protect ................................. 79 Reading ...................................................................... 75 Table Pointer Boundaries Based on Operation ........................ 74 Operations with TBLRD and TBLWT (table) ...... 74 Table Pointer Boundaries .......................................... 74 Table Reads and Table Writes .................................. 71 Write Sequence ......................................................... 77 Writing ........................................................................ 77 Protection Against Spurious Writes ................... 79 Unexpected Termination .................................... 79 Write Verify ........................................................ 79 FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 236
H
Hardware Multiplier ............................................................ 85 Introduction ................................................................ 85 Operation ................................................................... 85 Performance Comparison .......................................... 85
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MOVLW ................................................................... 241 MOVWF ................................................................... 241 MULLW .................................................................... 242 MULWF .................................................................... 242 NEGF ....................................................................... 243 NOP ......................................................................... 243 Opcode Field Descriptions ....................................... 216 POP ......................................................................... 244 PUSH ....................................................................... 244 RCALL ..................................................................... 245 RESET ..................................................................... 245 RETFIE .................................................................... 246 RETLW .................................................................... 246 RETURN .................................................................. 247 RLCF ........................................................................ 247 RLNCF ..................................................................... 248 RRCF ....................................................................... 248 RRNCF .................................................................... 249 SETF ........................................................................ 249 SETF (Indexed Literal Offset Mode) ........................ 263 SLEEP ..................................................................... 250 Standard Instructions ............................................... 215 SUBFWB .................................................................. 250 SUBLW .................................................................... 251 SUBWF .................................................................... 251 SUBWFB .................................................................. 252 SWAPF .................................................................... 252 TBLRD ..................................................................... 253 TBLWT ..................................................................... 254 TSTFSZ ................................................................... 255 XORLW .................................................................... 255 XORWF .................................................................... 256 INTCON Registers ....................................................... 95-97 Internal Oscillator Block ..................................................... 24 Adjustment ................................................................. 24 INTIO Modes .............................................................. 24 INTOSC Frequency Drift ............................................ 24 INTOSC Output Frequency ........................................ 24 OSCTUNE Register ................................................... 24 PLL in INTOSC Modes .............................................. 24 Internal RC Oscillator Use with WDT .......................................................... 202 Internet Address ............................................................... 314 Interrupt Sources .............................................................. 191 A/D Conversion Complete ....................................... 173 INTx Pin ................................................................... 105 PORTB, Interrupt-on-Change .................................. 105 TMR0 ....................................................................... 105 TMR1 Overflow ........................................................ 111 Interrupts ............................................................................ 93 Interrupts, Flag Bits Interrupt-on-Change Flag (RBIF Bit) .......................... 90 INTOSC, INTRC. See Internal Oscillator Block. IORLW ............................................................................. 238 IORWF ............................................................................. 238 IPR Registers ................................................................... 102
L
LFSR ................................................................................ 239 Low-Voltage Detect ......................................................... 187 Applications ............................................................. 190 Associated Registers ............................................... 190 Characteristics ......................................................... 283 Current Consumption ............................................... 189 Effects of a Reset .................................................... 190 Operation ................................................................. 188 During Sleep .................................................... 190 Setup ....................................................................... 189 Start-up Time ........................................................... 189 Typical Application ................................................... 190 Low-Voltage ICSP Programming. See Single-Supply ICSP Programming LVD. See Low-Voltage Detect. ........................................ 187
M
Master Clear (MCLR) ......................................................... 41 Memory Organization ........................................................ 51 Data Memory ............................................................. 57 Program Memory ....................................................... 51 Memory Programming Requirements .............................. 281 Microchip Internet Web Site ............................................. 314 Migration from Baseline to Enhanced Devices ................ 305 Migration from High-End to Enhanced Devices ............... 306 Migration from Mid-Range to Enhanced Devices ............ 306 MOVF .............................................................................. 239 MOVFF ............................................................................ 240 MOVLB ............................................................................ 240 MOVLW ........................................................................... 241 MOVSF ............................................................................ 259 MOVSS ............................................................................ 260 MOVWF ........................................................................... 241 MPLAB ASM30 Assembler, Linker, Librarian .................. 212 MPLAB ICD 2 In-Circuit Debugger .................................. 213 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ........................................................................ 213 MPLAB Integrated Development Environment Software . 211 MPLAB PM3 Device Programmer ................................... 213 MPLAB REAL ICE In-Circuit Emulator System ............... 213 MPLINK Object Linker/MPLIB Object Librarian ............... 212 MULLW ............................................................................ 242 MULWF ............................................................................ 242
N
NEGF ............................................................................... 243 NOP ................................................................................. 243
O
Oscillator Configuration ..................................................... 21 EC .............................................................................. 21 ECIO .......................................................................... 21 HS .............................................................................. 21 HSPLL ....................................................................... 21 Internal Oscillator Block ............................................. 24 INTIO1 ....................................................................... 21 INTIO2 ....................................................................... 21 LP .............................................................................. 21 RC ............................................................................. 21 RCIO .......................................................................... 21 XT .............................................................................. 21 Oscillator Selection .......................................................... 191 Oscillator Start-up Timer (OST) ................................... 29, 43 Oscillator Switching ........................................................... 26
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Oscillator Transitions ......................................................... 27 Oscillator, Timer1 ............................................................. 111
P
Packaging ........................................................................ 295 Details ...................................................................... 296 Marking Information ................................................. 295 PICSTART Plus Development Programmer .................... 214 PIE Registers ................................................................... 100 Pin Functions AVDD .......................................................................... 16 AVSS .......................................................................... 16 MCLR/VPP/RA5/FLTA ................................................ 13 NC .............................................................................. 16 RA0/AN0/INT0/KBI0/CMP0 ....................................... 14 RA1/AN1/INT1/KBI1 .................................................. 14 RA2/TX/CK ................................................................ 14 RA3/RX/DT ................................................................ 14 RA4/T0CKI/AN2//VREF+ ............................................. 14 RA6/OSC2/CLKO/T1OSO/T1CKI/AN3 ...................... 13 RA7/OSC1/CLKI/T1OSI/FLTA ................................... 13 RB0/PWM0 ................................................................ 15 RB1/PWM1 ................................................................ 15 RB2/INT2/KBI2/CMP2/T1OSO/T1CKI ....................... 15 RB3/INT3/KBI3/CMP1/T1OSI .................................... 15 RB4/PWM2 ................................................................ 15 RB5/PWM3 ................................................................ 15 RB6/PWM4/PGC ....................................................... 15 RB7/PWM5/PGD ....................................................... 15 VDD ............................................................................ 16 VSS ............................................................................. 16 Pinout I/O Descriptions PIC18F1230/1330 ...................................................... 13 PIR Registers ..................................................................... 98 PLL Frequency Multiplier ................................................... 23 HSPLL Oscillator Mode .............................................. 23 Use with INTOSC ....................................................... 23 POP ................................................................................. 244 POR. See Power-on Reset. PORTA Associated Registers ................................................. 89 LATA Register ............................................................ 87 PORTA Register ........................................................ 87 TRISA Register .......................................................... 87 PORTB Associated Registers ................................................. 92 Interrupt-on-Change Flag (RBIF Bit) .......................... 90 LATB Register ............................................................ 90 PORTB Register ........................................................ 90 TRISB Register .......................................................... 90 Power Control PWM ........................................................ 117 Associated Registers ............................................... 145 Control Registers ..................................................... 120 Functionality ............................................................. 120 Power-Managed Modes ..................................................... 31 and A/D Operation ................................................... 176 Clock Sources ............................................................ 31 Clock Transitions and Status Indicators ..................... 32 Effects on Clock Sources ........................................... 29 Entering ...................................................................... 31 Exiting Idle and Sleep Modes .................................... 37 By Interrupt ........................................................ 37 By Reset ............................................................ 37 By WDT Time-out .............................................. 37 Without an Oscillator Start-up Delay .................. 38 Idle Modes ................................................................. 35
PRI_IDLE .......................................................... 36 RC_IDLE ........................................................... 37 SEC_IDLE ......................................................... 36 Multiple Sleep Commands ......................................... 32 Run Modes ................................................................ 32 PRI_RUN ........................................................... 32 RC_RUN ............................................................ 33 SEC_RUN ......................................................... 32 Selecting .................................................................... 31 Sleep Mode ............................................................... 35 Summary (table) ........................................................ 31 Power-on Reset (POR) ...................................................... 41 Time-out Sequence ................................................... 43 Power-up Delays ............................................................... 29 Power-up Timer (PWRT) ................................................... 29 Prescaler, Timer0 ............................................................ 109 PRI_IDLE Mode ................................................................. 36 PRI_RUN Mode ................................................................. 32 Program Counter ............................................................... 52 PCL, PCH and PCU Registers .................................. 52 PCLATH and PCLATU Registers .............................. 52 Program Memory and Extended Instruction Set .................................... 69 Instructions ................................................................ 56 Two-Word .......................................................... 56 Interrupt Vector .......................................................... 51 Look-up Tables .......................................................... 54 Map and Stack (diagram) .......................................... 51 Reset Vector .............................................................. 51 Program Verification ........................................................ 207 Programming, Device Instructions ................................... 215 PUSH ............................................................................... 244 PUSH and POP Instructions .............................................. 53 PUSHL ............................................................................. 260 PWM Fault Input ................................................................ 142 Output and Polarity Control ..................................... 141 Single-Pulse Operation ............................................ 138 Special Event Trigger .............................................. 144 Update Lockout ....................................................... 144 PWM Dead-Time Decrementing the Counter ...................................... 136 Distortion ................................................................. 137 Generators ............................................................... 135 Insertion ................................................................... 135 Ranges .................................................................... 136 PWM Duty Cycle .............................................................. 131 Center-Aligned ......................................................... 133 Complementary Operation ...................................... 134 Edge-Aligned ........................................................... 132 Register Buffers ....................................................... 132 Registers ................................................................. 131 PWM Output Override ..................................................... 138 Complementary Mode ............................................. 138 Examples ................................................................. 140 Synchronization ....................................................... 138 PWM Period ..................................................................... 129 PWM Time Base .............................................................. 120 Continuous Up/Down Count Modes ........................ 125 Free-Running Mode ................................................. 125 Interrupts ................................................................. 125 In Continuous Up/Down Count Mode .............. 126 In Double Update Mode ................................... 128 In Free-Running Mode ..................................... 125 In Single-Shot Mode ........................................ 126
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Postscaler ................................................................ 125 Prescaler .................................................................. 125 Single-Shot Mode .................................................... 125 T1CON (Timer1 Control) ......................................... 111 TXSTA (Transmit Status and Control) ..................... 148 WDTCON (Watchdog Timer Control) ...................... 203 RESET ............................................................................. 245 Reset State of Registers .................................................... 46 Resets ........................................................................ 39, 191 Brown-out Reset (BOR) ........................................... 191 Oscillator Start-up Timer (OST) ............................... 191 Power-on Reset (POR) ............................................ 191 Power-up Timer (PWRT) ......................................... 191 RETFIE ............................................................................ 246 RETLW ............................................................................ 246 RETURN .......................................................................... 247 Return Address Stack ........................................................ 52 Associated Registers ................................................. 52 Return Stack Pointer (STKPTR) ........................................ 53 Revision History ............................................................... 303 RLCF ............................................................................... 247 RLNCF ............................................................................. 248 RRCF ............................................................................... 248 RRNCF ............................................................................ 249
R
RAM. See Data Memory. RBIF Bit .............................................................................. 90 RC Oscillator ...................................................................... 23 RCIO Oscillator Mode ................................................ 23 RC_IDLE Mode .................................................................. 37 RC_RUN Mode .................................................................. 33 RCALL .............................................................................. 245 RCON Register Bit Status During Initialization .................................... 46 Reader Response ............................................................ 315 Register File Summary ................................................. 61-63 Registers ADCON0 (A/D Control 0) ......................................... 169 ADCON1 (A/D Control 1) ......................................... 170 ADCON2 (A/D Control 2) ......................................... 171 BAUDCON (Baud Rate Control) .............................. 150 CMCON (Comparator Control) ................................ 179 CONFIG1H (Configuration 1 High) .......................... 192 CONFIG2H (Configuration 2 High) .......................... 194 CONFIG2L (Configuration 2 Low) ............................ 193 CONFIG3H (Configuration 3 High) .......................... 196 CONFIG3L (Configuration 3 Low) ............................ 195 CONFIG4L (Configuration 4 Low) ............................ 197 CONFIG5H (Configuration 5 High) .......................... 198 CONFIG5L (Configuration 5 Low) ............................ 198 CONFIG6H (Configuration 6 High) .......................... 199 CONFIG6L (Configuration 6 Low) ............................ 199 CONFIG7H (Configuration 7 High) .......................... 200 CONFIG7L (Configuration 7 Low) ............................ 200 CVRCON (Comparator Voltage Reference Control) 184 DEVID1 (Device ID 1) .............................................. 201 DEVID2 (Device ID 2) .............................................. 201 DTCON (Dead-Time Control) .................................. 136 EECON1 (EEPROM Control 1) ............................ 73, 82 FLTCONFIG (Fault Configuration) ........................... 143 INTCON (Interrupt Control) ........................................ 95 INTCON2 (Interrupt Control 2) ................................... 96 INTCON3 (Interrupt Control 3) ................................... 97 IPR1 (Peripheral Interrupt Priority 1) ........................ 102 IPR2 (Peripheral Interrupt Priority 2) ........................ 103 IPR3 (Peripheral Interrupt Priority 3) ........................ 103 LVDCON (Low-Voltage Detect Control) ................... 187 OSCCON (Oscillator Control) .................................... 28 OSCTUNE (Oscillator Tuning) ................................... 25 OVDCOND (Output Override Control) ..................... 140 OVDCONS (Output State) ....................................... 140 PIE1 (Peripheral Interrupt Enable 1) ........................ 100 PIE2 (Peripheral Interrupt Enable 2) ........................ 101 PIE3 (Peripheral Interrupt Enable 3) ........................ 101 PIR1 (Peripheral Interrupt Request (Flag) 1) ............. 98 PIR2 (Peripheral Interrupt Request (Flag) 2) ............. 99 PIR3 (Peripheral Interrupt Request (Flag) 3) ............. 99 PTCON0 (PWM Timer Control 0) ............................ 122 PTCON1 (PWM Timer Control 1) ............................ 122 PWMCON0 (PWM Control 0) .................................. 123 PWMCON1 (PWM Control 1) .................................. 124 RCON (Reset Control) ....................................... 40, 104 RCSTA (Receive Status and Control) ...................... 149 STATUS ..................................................................... 64 STKPTR (Stack Pointer) ............................................ 53 T0CON (Timer0 Control) .......................................... 107
S
SEC_IDLE Mode ............................................................... 36 SEC_RUN Mode ................................................................ 32 SETF ................................................................................ 249 Single-Supply ICSP Programming ................................... 210 Single-Supply ICSP Programming. SLEEP ............................................................................. 250 Sleep OSC1 and OSC2 Pin States ...................................... 29 Software Simulator (MPLAB SIM) ................................... 212 Special Features of the CPU ........................................... 191 Special Function Registers Map ............................................................................ 60 Stack Full/Underflow Resets .............................................. 54 SUBFSR .......................................................................... 261 SUBFWB ......................................................................... 250 SUBLW ............................................................................ 251 SUBULNK ........................................................................ 261 SUBWF ............................................................................ 251 SUBWFB ......................................................................... 252 SWAPF ............................................................................ 252
T
Table Reads/Table Writes ................................................. 54 TBLRD ............................................................................. 253 TBLWT ............................................................................. 254 Time-out in Various Situations (table) ................................ 43 Timer0 .............................................................................. 107 16-Bit Mode Timer Reads and Writes ...................... 109 Associated Registers ............................................... 109 Clock Source Edge Select (T0SE Bit) ..................... 109 Clock Source Select (T0CS Bit) ............................... 109 Interrupt ................................................................... 109 Operation ................................................................. 109 Prescaler ................................................................. 109 Switching the Assignment ............................... 109 Prescaler Assignment (PSA Bit) .............................. 109 Prescaler Select (T0PS2:T0PS0 Bits) ..................... 109 Prescaler. See Prescaler, Timer0.
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Timer1 .............................................................................. 111 16-Bit Read/Write Mode ........................................... 114 Associated Registers ............................................... 115 Interrupt .................................................................... 114 Operation ................................................................. 112 Oscillator .......................................................... 111, 113 Oscillator Layout Considerations ............................. 113 Overflow Interrupt .................................................... 111 TMR1H Register ...................................................... 111 TMR1L Register ....................................................... 111 Use as a Clock Source ............................................ 113 Use as a Real-Time Clock ....................................... 114 Timing Diagrams A/D Conversion ........................................................ 293 Asynchronous Reception ......................................... 161 Asynchronous Transmission .................................... 158 Asynchronous Transmission (Back-to-Back) ........... 158 Automatic Baud Rate Calculation ............................ 156 Auto-Wake-up Bit (WUE) During Normal Operation 162 Auto-Wake-up Bit (WUE) During Sleep ................... 162 BRG Overflow Sequence ......................................... 156 Brown-out Reset (BOR) ........................................... 289 CLKO and I/O .......................................................... 288 Clock/Instruction Cycle .............................................. 55 Dead-Time Insertion for Complementary PWM ....... 135 Duty Cycle Update Times in Continuous Up/Down Count Mode ................................................................ 132 Duty Cycle Update Times in Continuous Up/Down Count Mode with Double Updates .............................. 133 Edge-Aligned PWM .................................................. 132 EUSART Synchronous Receive (Master/Slave) ...... 291 EUSART Synchronous Transmission (Master/Slave) .... 291 External Clock (All Modes Except PLL) ................... 286 Fail-Safe Clock Monitor ............................................ 206 Low-Voltage Detect Characteristics ......................... 283 Low-Voltage Detect Operation ................................. 189 Override Bits in Complementary Mode .................... 139 PWM Output Override Example #1 .......................... 141 PWM Output Override Example #2 .......................... 141 PWM Period Buffer Updates in Continuous Up/Down Count Modes ................................................... 130 PWM Period Buffer Updates in Free-Running Mode 130 PWM Time Base Interrupt (Free-Running Mode) .... 126 PWM Time Base Interrupt (Single-Shot Mode) ........ 127 PWM Time Base Interrupts (Continuous Up/Down Count Mode with Double Updates) ............................ 128 PWM Time Base Interrupts (Continuous Up/Down Count Mode) ............................................................... 127 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST), Power-up Timer (PWRT) ...................... 289 Send Break Character Sequence ............................ 163 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................................................ 45 Start of Center-Aligned PWM ................................... 133 Synchronous Reception (Master Mode, SREN) ...... 166 Synchronous Transmission ...................................... 164 Synchronous Transmission (Through TXEN) .......... 165 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) ............................................................... 45 Time-out Sequence on Power-up (MCLR Not Tied to VDD, Case 1) ...................................................... 44 Time-out Sequence on Power-up (MCLR Not Tied to VDD, Case 2) ...................................................... 44 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise < TPWRT) ............................................ 44 Timer0 and Timer1 External Clock .......................... 290 Transition for Entry to Idle Mode ............................... 36 Transition for Entry to SEC_RUN Mode .................... 33 Transition for Entry to Sleep Mode ............................ 35 Transition for Two-Speed Start-up (INTOSC to HSPLL) 204 Transition for Wake From Idle to Run Mode .............. 36 Transition for Wake From Sleep (HSPLL) ................. 35 Transition from RC_RUN Mode to PRI_RUN Mode .. 34 Transition from SEC_RUN Mode to PRI_RUN Mode (HSPLL) ............................................................. 33 Transition to RC_RUN Mode ..................................... 34 Timing Diagrams and Specifications ............................... 286 CLKO and I/O Requirements ................................... 288 EUSART Synchronous Receive Requirements ....... 291 EUSART Synchronous Transmission Requirements .... 291 External Clock Requirements .................................. 286 PLL Clock ................................................................ 287 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements .. 289 Timer0 and Timer1 External Clock Requirements ... 290 Top-of-Stack Access .......................................................... 52 TSTFSZ ........................................................................... 255 Two-Speed Start-up ................................................. 191, 204 Two-Word Instructions Example Cases ......................................................... 56 TXSTA Register BRGH Bit ................................................................. 151
V
Voltage Reference Specifications .................................... 282
W
Watchdog Timer (WDT) ........................................... 191, 202 Associated Registers ............................................... 203 Control Register ....................................................... 202 During Oscillator Failure .......................................... 205 Programming Considerations .................................. 202 WWW Address ................................................................ 314 WWW, On-Line Support ...................................................... 7
X
XORLW ........................................................................... 255 XORWF ........................................................................... 256
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NOTES:
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2009 Microchip Technology Inc.
PIC18F1230/1330
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
2009 Microchip Technology Inc.
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PIC18F1230/1330
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC18F1230/1330 Questions: 1. What are the best features of this document? Y N Literature Number: DS39758D FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
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PIC18F1230/1330
PIC18F1230/1330 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device PIC18F1230/1330(1) PIC18F1230/1330T(2) VDD range 4.2V to 5.5V PIC18LF1230/1330(1) PIC18LF1230/1330T(2) VDD range 2.0V to 5.5V I E SO SS P ML = = = = = = -40C to +85C (Industrial) -40C to +125C (Extended) Plastic Small Outline (SOIC) Plastic Shrink Small Outline (SSOP) Plastic Dual In-line (PDIP) Plastic Quad Flat No Lead (QFN) PIC18LF1330-I/P 301 = Industrial temp., PDIP package, Extended VDD limits, QTP pattern #301. PIC18LF1230-I/SO = Industrial temp., SOIC package, Extended VDD limits.
Temperature Range
Package
Note 1: 2:
F = Standard Voltage Range LF = Wide Voltage Range T = in tape and reel
Pattern
QTP, SQTP, Code or Special Requirements (blank otherwise)
2009 Microchip Technology Inc.
DS39758D-page 317
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
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EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
03/26/09
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2009 Microchip Technology Inc.

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